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kntran1
2026-03-23 14:40:39 -05:00
parent e84b2b4166
commit 4e2a5258a5
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41
bootloader/mcuboot/boot/cypress/.gitignore vendored Normal file
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outdir/
.*.swp
target.sh
*.pyc
tags
rusty-tags.*
# mynewt
/repos/
/project.state
/bin/
/targets/
**/build/**/*
#Eclipse project files
.cproject
.project
# Compiled python modules.
*.pyc
# Setuptools distribution folder.
/scripts/dist/
# Python egg metadata, regenerated from source files by setuptools.
/scripts/*.egg-info
/scripts/*.egg
# Build dirs
*out/*/*
*out/obj/*
# Build files
*.o
*.d
*.map
*.elf
*.bin
*.hex
*.log
*.lst

132
bootloader/mcuboot/boot/cypress/BlinkyApp/BlinkyApp.mk Normal file
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################################################################################
# \file BlinkyApp.mk
# \version 1.0
#
# \brief
# Makefile to describe demo application BlinkyApp for Cypress MCUBoot based applications.
#
################################################################################
# \copyright
# Copyright 2018-2019 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
################################################################################
include host.mk
# Cypress' MCUBoot Application supports GCC ARM only at this moment
# Set defaults to:
# - compiler GCC
# - build configuration to Debug
# - image type to BOOT
COMPILER ?= GCC_ARM
IMG_TYPE ?= BOOT
# For which core this application is built
CORE ?= CM4
# image type can be BOOT or UPGRADE
IMG_TYPES = BOOT UPGRADE
# possible values are 0 and 0xff
# internal Flash by default
ERASED_VALUE ?= 0
ifneq ($(COMPILER), GCC_ARM)
$(error Only GCC ARM is supported at this moment)
endif
CUR_APP_PATH = $(PRJ_DIR)/$(APP_NAME)
include $(PRJ_DIR)/platforms.mk
include $(PRJ_DIR)/common_libs.mk
include $(PRJ_DIR)/toolchains.mk
# Application-specific DEFINES
ifeq ($(IMG_TYPE), BOOT)
DEFINES_APP := -DBOOT_IMG
else
DEFINES_APP := -DUPGRADE_IMG
endif
# Define start of application, RAM start and size, slot size
ifeq ($(PLATFORM), PSOC_062_2M)
DEFINES_APP += -DRAM_START=0x08040000
DEFINES_APP += -DRAM_SIZE=0x10000
else ifeq ($(PLATFORM), PSOC_062_1M)
DEFINES_APP += -DRAM_START=0x08020000
DEFINES_APP += -DRAM_SIZE=0x10000
else ifeq ($(PLATFORM), PSOC_062_512K)
DEFINES_APP += -DRAM_START=0x08020000
DEFINES_APP += -DRAM_SIZE=0x10000
endif
DEFINES_APP += -DRAM_SIZE=0x10000
DEFINES_APP += -DUSER_APP_START=0x10018000
SLOT_SIZE ?= 0x10000
# Collect Test Application sources
SOURCES_APP_SRC := $(wildcard $(CUR_APP_PATH)/*.c)
# Collect all the sources
SOURCES_APP += $(SOURCES_APP_SRC)
# Collect includes for BlinkyApp
INCLUDE_DIRS_APP := $(addprefix -I, $(CURDIR))
INCLUDE_DIRS_APP += $(addprefix -I, $(CUR_APP_PATH))
# Overwite path to linker script if custom is required, otherwise default from BSP is used
ifeq ($(COMPILER), GCC_ARM)
LINKER_SCRIPT := $(subst /cygdrive/c,c:,$(CUR_APP_PATH)/linker/$(APP_NAME).ld)
else
$(error Only GCC ARM is supported at this moment)
endif
ASM_FILES_APP :=
ASM_FILES_APP += $(ASM_FILES_STARTUP)
# We still need this for MCUBoot apps signing
IMGTOOL_PATH ?= ../../scripts/imgtool.py
SIGN_ARGS := sign --header-size 1024 --pad-header --align 8 -v "2.0" -S $(SLOT_SIZE) -M 512 --overwrite-only -R $(ERASED_VALUE) -k keys/$(SIGN_KEY_FILE).pem
# Output folder
OUT := $(APP_NAME)/out
# Output folder to contain build artifacts
OUT_TARGET := $(OUT)/$(PLATFORM)
OUT_CFG := $(OUT_TARGET)/$(BUILDCFG)
# Set build directory for BOOT and UPGRADE images
ifeq ($(IMG_TYPE), UPGRADE)
ifeq ($(ENC_IMG), 1)
SIGN_ARGS += --encrypt ../../$(ENC_KEY_FILE).pem
endif
SIGN_ARGS += --pad
UPGRADE_SUFFIX :=_upgrade
OUT_CFG := $(OUT_CFG)/upgrade
else
OUT_CFG := $(OUT_CFG)/boot
endif
pre_build:
$(info [PRE_BUILD] - Generating linker script for application $(CUR_APP_PATH)/linker/$(APP_NAME).ld)
@$(CC) -E -x c $(CFLAGS) $(INCLUDE_DIRS) $(CUR_APP_PATH)/linker/$(APP_NAME)_template.ld | grep -v '^#' >$(CUR_APP_PATH)/linker/$(APP_NAME).ld
# Post build action to execute after main build job
post_build: $(OUT_CFG)/$(APP_NAME).hex
$(info [POST_BUILD] - Executing post build script for $(APP_NAME))
mv -f $(OUT_CFG)/$(APP_NAME).hex $(OUT_CFG)/$(APP_NAME)_unsigned.hex
$(PYTHON_PATH) $(IMGTOOL_PATH) $(SIGN_ARGS) $(OUT_CFG)/$(APP_NAME)_unsigned.hex $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).hex

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bootloader/mcuboot/boot/cypress/BlinkyApp/BlinkyApp_CM4_Debug.launch Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${cy_tools_path:openocd}/bin/openocd"/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-s &quot;${cy_tools_path:openocd}/scripts&quot;&#13;&#10;-s &quot;${workspace_loc}/BlinkyLED_config/GeneratedSource&quot;&#13;&#10;-c &quot;source [find interface/kitprog3.cfg]&quot;&#13;&#10;-c &quot;source [find target/psoc6_2m.cfg]&quot;&#13;&#10;-c &quot;gdb_port 3332&quot;&#13;&#10;-c &quot;puts stderr {Started by GNU MCU Eclipse}&quot;&#13;&#10;-c &quot;init; reset init&quot;"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="/Users/rnok/repos/cy_mcuboot_project/cy_mcuboot/boot/cypress/BlinkyApp/out/boot/CY8CKIT-064S2-4343W/Debug/BlinkyApp.elf"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="false"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value="/Users/rnok/repos/cy_mcuboot_project/cy_mcuboot/boot/cypress/BlinkyApp/out/CY8CKIT-064S2-4343W/Debug/boot/BlinkyApp.elf"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cy_sdk_install_dir}/tools/gcc-7.2.1-1.0/bin/arm-none-eabi-gdb${cy_exe_platform_ext}"/>
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="boot/cypress/BlinkyApp/out/PSOC_062_2M/Debug/boot/BlinkyApp.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="cy_mcuboot"/>
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.1139973781"/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/cy_mcuboot"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;&gt;&#10;&lt;memoryBlockExpression address=&quot;268566528&quot; label=&quot;0x10020000&quot;/&gt;&#10;&lt;memoryBlockExpression address=&quot;268632064&quot; label=&quot;0x10030000&quot;/&gt;&#10;&lt;/memoryBlockExpressionList&gt;&#10;"/>
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
</launchConfiguration>

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bootloader/mcuboot/boot/cypress/BlinkyApp/Readme.md Normal file
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### Blinking LED test application for MCUboot bootloader
### Description
Implements simple Blinky LED CM4 application to demonstrate MCUboot Application operation in terms of BOOT and UPGRADE process.
It is started by MCUboot Application which is running on CM0p.
Functionality:
* Blinks RED led with 2 different rates, depending on type of image - BOOT or UPGRADE.
* Prints debug info and version of itself to terminal at 115200 baud.
* Can be built for BOOT slot or UPGRADE slot of bootloader.
Currently supported platforms
* PSOC_062_2M
* PSOC_062_1M
* PSOC_062_512K
### Hardware limitations
Since this application is created to demonstrate MCUboot library features and not as reference examples some considerations are taken.
1. Port/pin `P5_0` and `P5_1` used to configure serial port for debug prints. These pins are the most commonly used for serial port connection among available Cypress PSoC 6 kits. If you try to use custom hardware with this application - change definitions of `CY_DEBUG_UART_TX` and `CY_DEBUG_UART_RX` in `main.c` of BlinkyApp to port/pin pairs corresponding to your design.
2. Port `GPIO_PRT13` pin `7U` used to define user connection LED. This pin is the most commonly used for USER_LED connection among available Cypress PSoC 6 kits. If you try to use custom hardware with this application - change definitions of `LED_PORT` and `LED_PIN` in `main.c` of BlinkyApp to port/pin pairs corresponding to your design.
### Pre-build action
Pre-build action is implemented for defining start address and size of flash, as well as RAM start address and size for BlinkyApp.
These values are set by specifing following macros: `-DUSER_APP_SIZE`, `-DUSER_APP_START`, `-DRAM_SIZE`, `-DRAM_START` in makefile.
Pre-build action calls GCC preprocessor which intantiates defines for particular values in `BlinkyApp_template.ld`.
Default values set for currently supported targets:
* `BlinkyApp.mk` to `-DUSER_APP_START=0x10018000`
**Important**: make sure RAM areas of CM4-based BlinkyApp and CM0p-based MCUBootApp bootloader do not overlap.
Memory (stack) corruption of CM0p application can cause failure if SystemCall-served operations invoked from CM4.
### Building an application
Root directory for build is **boot/cypress.**
The following command will build regular HEX file of a BlinkyApp for BOOT slot. Substitute `PLATFORM=` to a paltform name you use in all following commands.
make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT
This have following defaults suggested:
BUILDCFG=Debug
IMG_TYPE=BOOT
To build UPGRADE image use following command:
make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x10000
Note: HEADER_OFFSET=%SLOT_SIZE%
Example command-line for single-image:
make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT
**Building Multi-Image**
`BlinkyApp` can be built to use in multi-image bootloader configuration.
To get appropriate artifacts to use with multi image MCUBootApp, makefile flag `HEADER_OFFSET=` can be used.
Example usage:
Considering default config:
* first image BOOT (PRIMARY) slot start `0x10018000`
* slot size `0x10000`
* second image BOOT (PRIMARY) slot start `0x10038000`
To get appropriate artifact for second image PRIMARY slot run this command:
make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT HEADER_OFFSET=0x20000
*Note:* only 2 images are supported at the moment.
**How to build upgrade image for external memory:**
To prepare MCUBootApp for work with external memory please refer to `MCUBootApp/ExternalMemory.md`.
For build BlinkyApp upgrade image for external memory use command:
make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x7FE8000 ERASED_VALUE=0xff
`HEADER_OFFSET` defines the offset from original boot image address. This one in line above suggests secondary slot will start from `0x18000000`.
`ERASED_VALUE` defines the memory cell contents in erased state. It is `0x00` for PSoC6's internal Flash and `0xff` for S25FL512S.
In case of using muti-image configuration, upgrade image for second application can be built using next command:
make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x8028000 ERASED_VALUE=0xff
Note: for S25FL512S block address shuld be mutiple by 0x40000
**How to build encrypted upgrade image :**
To prepare MCUBootApp for work with encrypted upgrade image please refer to `MCUBootApp/Readme.md`.
To obtain encrypted upgrade image of BlinkyApp extra flag `ENC_IMG=1` should be passed in command line, for example:
make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x20000 ENC_IMG=1
This also suggests user already placed corresponing `*.pem` key in `\keys` folder. The key variables are defined in root `Makefile` as `SIGN_KEY_FILE` and `ENC_KEY_FILE`
### Post-build
Post build action is executed at compile time for `BlinkyApp`. In case of build for `PSOC_062_2M` platform it calls `imgtool` from `MCUboot` scripts and adds signature to compiled image.
Flags passed to `imgtool` for signature are defined in `SIGN_ARGS` variable in BlinkyApp.mk.
### How to program an application
Use any preferred tool for programming hex files.
Hex file names to use for programming:
`BlinkyApp` always produce build artifacts in 2 separate folders - `boot` and `upgrade`.
`BlinkyApp` built to run with `MCUBootApp` produces files with name BlinkyApp.hex in `boot` directory and `BlinkyApp_upgrade.hex` in `upgrade` folder. These files are ready to be flashed to the board.
`BlinkyApp_unsigned.hex` hex file is also preserved in both cases for possible troubleshooting.
Files to use for programming are:
`BOOT` - boot/BlinkyApp.hex
`UPGRADE` - upgrade/BlinkyApp_upgrade.hex
**Flags:**
- `BUILDCFG` - configuration **Release** or **Debug**
- `MAKEINFO` - 0 (default) - less build info, 1 - verbose output of compilation.
- `HEADER_OFFSET` - 0 (default) - no offset of output hex file, 0x%VALUE% - offset for output hex file. Value 0x10000 is slot size MCUboot Bootloader in this example.
- `IMG_TYPE` - `BOOT` (default) - build image for BOOT slot of MCUboot Bootloader, `UPGRADE` - build image for UPGRADE slot of MCUboot Bootloader.
- `ENC_IMG` - 0 (default) - build regular upgrade image, `1` - build encrypted upgrade image (MCUBootApp should also be built with this flash set 1)
**NOTE**: In case of `UPGRADE` image `HEADER_OFFSET` should be set to MCUboot Bootloader slot size.
### Example terminal output
When user application programmed in BOOT slot:
===========================
[BlinkyApp] BlinkyApp v1.0 [CM4]
===========================
[BlinkyApp] GPIO initialized
[BlinkyApp] UART initialized
[BlinkyApp] Retarget I/O set to 115200 baudrate
[BlinkyApp] Red led blinks with 1 sec period
When user application programmed in UPRADE slot and upgrade procedure was successful:
===========================
[BlinkyApp] BlinkyApp v2.0 [+]
===========================
[BlinkyApp] GPIO initialized
[BlinkyApp] UART initialized
[BlinkyApp] Retarget I/O set to 115200 baudrate
[BlinkyApp] Red led blinks with 0.25 sec period

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bootloader/mcuboot/boot/cypress/BlinkyApp/libs.mk Normal file
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################################################################################
# \file libs.mk
# \version 1.0
#
# \brief
# Makefile to describe libraries needed for Cypress MCUBoot based applications.
#
################################################################################
# \copyright
# Copyright 2018-2019 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
################################################################################
################################################################################
# PDL library
################################################################################
PDL_VERSION = 121
#
CUR_LIBS_PATH = $(PRJ_DIR)/libs
# Collect source files for Retarget-io
SOURCES_RETARGET_IO := $(wildcard $(CUR_LIBS_PATH)/retarget-io/*.c)
SOURCES_WATCHDOG := $(wildcard $(CUR_LIBS_PATH)/watchdog/*.c)
# Collect source files for HAL
SOURCES_HAL := $(wildcard $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/source/*.c)
SOURCES_HAL += $(wildcard $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/source/triggers/*.c)
SOURCES_HAL += $(wildcard $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/source/pin_packages/*.c)
# Retarget-io related include directories
INCLUDE_DIRS_RETARGET_IO := $(CUR_LIBS_PATH)/retarget-io
INCLUDE_DIRS_WATCHDOG := $(CUR_LIBS_PATH)/watchdog
# Collect dirrectories containing headers for PSOC6 HAL
INCLUDE_DIRS_HAL := $(CUR_LIBS_PATH)/psoc6hal/include
INCLUDE_DIRS_HAL += $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/include
INCLUDE_DIRS_HAL += $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/include/pin_packages
INCLUDE_DIRS_HAL += $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/include/triggers
# Collected source files for libraries
SOURCES_LIBS += $(SOURCES_RETARGET_IO)
SOURCES_LIBS += $(SOURCES_WATCHDOG)
SOURCES_LIBS += $(SOURCES_HAL)
# Collected include directories for libraries
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_RETARGET_IO))
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_WATCHDOG))
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_HAL))

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bootloader/mcuboot/boot/cypress/BlinkyApp/linker/BlinkyApp_template.ld Normal file
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/***************************************************************************//**
* \file cy8c6xxa_cm4_dual.ld
* \version 2.60
*
* Linker file for the GNU C compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point location is fixed and starts at 0x10000000. The valid
* application image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include <main.h>
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* Size of the stack section at the end of CM4 SRAM */
STACK_SIZE = 0x1000;
/* The size of the MCU boot header area at the start of FLASH */
BOOT_HEADER_SIZE = 0x400;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
* EXTERN multiple times. This command has the same effect as the -u command-line
* option.
*/
EXTERN(Reset_Handler)
/* The MEMORY section below describes the location and size of blocks of memory in the target.
* Use this section to specify the memory regions available for allocation.
*/
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing the 'ram' and 'flash' regions.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
*/
ram (rwx) : ORIGIN = RAM_START, LENGTH = RAM_SIZE
flash (rx) : ORIGIN = USER_APP_START, LENGTH = USER_APP_SIZE
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
/* The following regions define device specific memory regions and must not be changed. */
sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
SECTIONS
{
/* Cortex-M4 application flash area */
.text ORIGIN(flash) + BOOT_HEADER_SIZE :
{
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))
. = ALIGN(4);
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
/* Read-only code (constants). */
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.eh_frame*))
} > flash
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > flash
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > flash
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy interrupt vectors from flash to RAM */
LONG (__Vectors) /* From */
LONG (__ram_vectors_start__) /* To */
LONG (__Vectors_End - __Vectors) /* Size */
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG (__data_end__ - __data_start__) /* Size */
__copy_table_end__ = .;
} > flash
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > flash
__etext = . ;
.ramVectors (NOLOAD) : ALIGN(8)
{
__ram_vectors_start__ = .;
KEEP(*(.ram_vectors))
__ram_vectors_end__ = .;
} > ram
.data __ram_vectors_end__ : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
KEEP(*(.cy_ramfunc*))
. = ALIGN(4);
__data_end__ = .;
} > ram
/* Place variables in the section that should not be initialized during the
* device startup.
*/
.noinit (NOLOAD) : ALIGN(8)
{
KEEP(*(.noinit))
} > ram
/* The uninitialized global or static variables are placed in this section.
*
* The NOLOAD attribute tells linker that .bss section does not consume
* any space in the image. The NOLOAD attribute changes the .bss type to
* NOBITS, and that makes linker to A) not allocate section in memory, and
* A) put information to clear the section with all zeros during application
* loading.
*
* Without the NOLOAD attribute, the .bss section might get PROGBITS type.
* This makes linker to A) allocate zeroed section in memory, and B) copy
* this section to RAM during application loading.
*/
.bss (NOLOAD):
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram
.heap (NOLOAD):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
__HeapLimit = .;
} > ram
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
KEEP(*(.stack*))
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Used for the digital signature of the secure application and the Bootloader SDK application.
* The size of the section depends on the required data size. */
.cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
{
KEEP(*(.cy_app_signature))
} > flash
/* Emulated EEPROM Flash area */
.cy_em_eeprom :
{
KEEP(*(.cy_em_eeprom))
} > em_eeprom
/* Supervisory Flash: User data */
.cy_sflash_user_data :
{
KEEP(*(.cy_sflash_user_data))
} > sflash_user_data
/* Supervisory Flash: Normal Access Restrictions (NAR) */
.cy_sflash_nar :
{
KEEP(*(.cy_sflash_nar))
} > sflash_nar
/* Supervisory Flash: Public Key */
.cy_sflash_public_key :
{
KEEP(*(.cy_sflash_public_key))
} > sflash_public_key
/* Supervisory Flash: Table of Content # 2 */
.cy_toc_part2 :
{
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
/* Supervisory Flash: Table of Content # 2 Copy */
.cy_rtoc_part2 :
{
KEEP(*(.cy_rtoc_part2))
} > sflash_rtoc_2
/* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details.
*/
.cy_xip :
{
KEEP(*(.cy_xip))
} > xip
/* eFuse */
.cy_efuse :
{
KEEP(*(.cy_efuse))
} > efuse
/* These sections are used for additional metadata (silicon revision,
* Silicon/JTAG ID, etc.) storage.
*/
.cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
}
/* The following symbols used by the cymcuelftool. */
/* Flash */
__cy_memory_0_start = 0x10000000;
__cy_memory_0_length = 0x00200000;
__cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
__cy_memory_1_start = 0x14000000;
__cy_memory_1_length = 0x8000;
__cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
__cy_memory_2_start = 0x16000000;
__cy_memory_2_length = 0x8000;
__cy_memory_2_row_size = 0x200;
/* XIP */
__cy_memory_3_start = 0x18000000;
__cy_memory_3_length = 0x08000000;
__cy_memory_3_row_size = 0x200;
/* eFuse */
__cy_memory_4_start = 0x90700000;
__cy_memory_4_length = 0x100000;
__cy_memory_4_row_size = 1;
/* EOF */

136
bootloader/mcuboot/boot/cypress/BlinkyApp/main.c Normal file
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/*
* Copyright (c) 2020 Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
/*******************************************************************************/
#include "system_psoc6.h"
#include "cy_pdl.h"
#include "cyhal.h"
#include "cy_retarget_io.h"
#include "watchdog.h"
/* Define pins for UART debug output */
#define CY_DEBUG_UART_TX (P5_1)
#define CY_DEBUG_UART_RX (P5_0)
#if defined(PSOC_062_2M)
#warning "Check if User LED is correct for your target board."
#define LED_PORT GPIO_PRT13
#define LED_PIN 7U
#elif defined(PSOC_062_1M)
#define LED_PORT GPIO_PRT13
#define LED_PIN 7U
#elif defined(PSOC_062_512K)
#define LED_PORT GPIO_PRT11
#define LED_PIN 1U
#endif
#define LED_NUM 5U
#define LED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define LED_INIT_DRIVESTATE 1
const cy_stc_gpio_pin_config_t LED_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = HSIOM_SEL_GPIO,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#define WATCHDOG_UPD_MESSAGE "[BlinkyApp] Update watchdog timer started in MCUBootApp to mark successful start of user app\r\n"
#define WATCHDOG_FREE_MESSAGE "[BlinkyApp] Turn off watchdog timer\r\n"
#ifdef BOOT_IMG
#define BLINK_PERIOD (1000u)
#define GREETING_MESSAGE_VER "[BlinkyApp] BlinkyApp v1.0 [CM4]\r\n"
#define GREETING_MESSAGE_INFO "[BlinkyApp] Red led blinks with 1 sec period\r\n"
#elif defined(UPGRADE_IMG)
#define BLINK_PERIOD (250u)
#define GREETING_MESSAGE_VER "[BlinkyApp] BlinkyApp v2.0 [+]\r\n"
#define GREETING_MESSAGE_INFO "[BlinkyApp] Red led blinks with 0.25 sec period\r\n"
#else
#error "[BlinkyApp] Please specify type of image: -DBOOT_IMG or -DUPGRADE_IMG\r\n"
#endif
void check_result(int res)
{
if (res != CY_RSLT_SUCCESS) {
CY_ASSERT(0);
}
}
void test_app_init_hardware(void)
{
/* enable interrupts */
__enable_irq();
/* Disabling watchdog so it will not interrupt normal flow later */
Cy_GPIO_Pin_Init(LED_PORT, LED_PIN, &LED_config);
/* Initialize retarget-io to use the debug UART port */
check_result(cy_retarget_io_init(CY_DEBUG_UART_TX, CY_DEBUG_UART_RX,
CY_RETARGET_IO_BAUDRATE));
printf("\n===========================\r\n");
printf(GREETING_MESSAGE_VER);
printf("===========================\r\n");
printf("[BlinkyApp] GPIO initialized \r\n");
printf("[BlinkyApp] UART initialized \r\n");
printf("[BlinkyApp] Retarget I/O set to 115200 baudrate \r\n");
}
int main(void)
{
uint32_t blinky_period = BLINK_PERIOD;
test_app_init_hardware();
printf(GREETING_MESSAGE_INFO);
/* Update watchdog timer to mark successful start up of application */
printf(WATCHDOG_UPD_MESSAGE);
cy_wdg_kick();
printf(WATCHDOG_FREE_MESSAGE);
cy_wdg_free();
for (;;)
{
/* Toggle the user LED periodically */
Cy_SysLib_Delay(blinky_period/2);
/* Invert the USER LED state */
Cy_GPIO_Inv(LED_PORT, LED_PIN);
}
return 0;
}

25
bootloader/mcuboot/boot/cypress/BlinkyApp/main.h Normal file
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/*
\copyright
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef USER_APP_START
#define USER_APP_START 0x10000000
#endif
#ifndef USER_APP_SIZE
#define USER_APP_SIZE 0x10000
#endif

100
bootloader/mcuboot/boot/cypress/MCUBootApp/ExternalMemory.md Normal file
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### External Memory support for Secondary Slot
**Description**
Given document describes the use of external memory module as a secondary (upgrade) slot with Cypress' PSoC6 devices.
The demonstration device is CY8CPROTO-062-4343W board which is PSoC6 device with 2M of Flash available.
The memory module present on board is S25FL512SAGMFI010 512-Mbit external Quad SPI NOR Flash.
Using external memory for secondary slot allows to nearly double the size of Boot Image.
**Operation Design and Flow**
The design is based on using SFDP command's auto-discovery functionality of memory module IC and Cypress' SMIF PDL driver.
It is assumed that user's design meets following:
* The memory-module used is SFDP-compliant;
* There only one module is being used for secondary slot;
* Only "OWERWRITE" bootloading scheme is used;
* The address for secondary slot should start from 0x18000000.
This corresponds to PSoC6's SMIF (Serial Memory InterFace) IP block mapping.
* The slot size for upgrade slot is even (or smaller) to erase size (0x40000) of given memory module.
This requirement is accepted for code simplicity.
The default flash map implemented is the following:
Single-image mode.
`[0x10000000, 0x10018000]` - MCUBootApp (bootloader) area;
`[0x10018000, 0x10028000]` - primary slot for BlinkyApp;
`[0x18000000, 0x18010000]` - secondary slot for BlinkyApp;
`[0x10038000, 0x10039000]` - scratch area (not used);
Multi(dual)-image mode.
`[0x10000000, 0x10018000]` - MCUBootApp (bootloader) area;
`[0x10018000, 0x10028000]` - primary1 slot for BlinkyApp;
`[0x18000000, 0x18010000]` - secondary1 slot for BlinkyApp;
`[0x10038000, 0x10048000]` - primary2 slot for user app ;
`[0x18040000, 0x18050000]` - secondary2 slot for user app;
`[0x10058000, 0x10059000]` - scratch area (not used);
Size of slots `0x10000` - 64kB
**Note 1**: make sure primary, secondary slot and bootloader app sizes are appropriate and correspond to flash area size defined in Applications' linker files.
**Note 2**: make sure secondary slot start address is aligned (or smaller) to erase size (0x40000 - 256kB).
MCUBootApp's `main.c` contains the call to Init-SFDP API which performs required GPIO configurations, SMIF IP block configurations, SFDP protocol read and memory-config structure initialization.
After that MCUBootApp is ready to accept upgrade image from external memory module.
Once valid upgrade image was accepted the image in external memory will be erased.
**How to enable external memory support:**
1. Pass `USE_EXTERNAL_FLASH=1` flag to `make` command when building MCUBootApp.
2. Navigate to `cy_flash_map.c` and check if secondary slot start address and size meet the application's needs.
3. Define which slave select is used for external memory on a board by setting `smif_id` value in `main.c`.
4. Build MCUBootApp as described in `Readme.md`.
**Note 3**: External memory code is developed basing on PDL and can be run on CM0p core only. It may require modifications if used on CM4.
**How to build upgrade image for external memory:**
make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x7FE8000 ERASED_VALUE=0xff
`HEADER_OFFSET` defines the offset from original boot image address. This one in line above suggests secondary slot will start from `0x18000000`.
`ERASED_VALUE` defines the memory cell contents in erased state. It is `0x00` for PSoC6's internal Flash and `0xff` for S25FL512S.
**Programming to external memory**
The MCUBootApp programming can be done similarly to described in `Readme.md`:
export OPENOCD=/Applications/ModusToolbox/tools_2.1/openocd
${OPENOCD}/bin/openocd -s ${OPENOCD}/scripts \
-f ${OPENOCD}/scripts/interface/kitprog3.cfg \
-f ${OPENOCD}/scripts/target/psoc6_2m.cfg \
-c "init; psoc6 sflash_restrictions 1" \
-c "init; reset init; program PATH_TO_APPLICATION.hex" \
-c "resume; reset; exit"
There is a NULL-pointer placed for SMIF configuration pointer in TOC2 (Table Of Contents, `cy_serial_flash_prog.c`).
This is done to force CY8PROTO-062-4343W DAP Link firmware to program external memory with hardcoded values.
1. Press SW3 Mode button on a board to switch the board into DAP Link mode.
2. Once DAP Link removable disk appeared drop (copy) the upgrade image HEX file to it.
This will invoke firmware to program external memory.
**Note 3:** the programming of external memory is limited to S25FL512S p/n only at this moment.

418
bootloader/mcuboot/boot/cypress/MCUBootApp/MCUBootApp.ld Normal file
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/***************************************************************************//**
* \file cy8c6xxa_cm0plus.ld
* \version 2.60
*
* Linker file for the GNU C compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point location is fixed and starts at 0x10000000. The valid
* application image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* Size of the stack section at the end of CM0+ SRAM */
STACK_SIZE = 0x1000;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
* EXTERN multiple times. This command has the same effect as the -u command-line
* option.
*/
EXTERN(Reset_Handler)
/* The MEMORY section below describes the location and size of blocks of memory in the target.
* Use this section to specify the memory regions available for allocation.
*/
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
* You can change the memory allocation by editing the 'ram' and 'flash' regions.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'.
*/
public_ram (rw) : ORIGIN = 0x08000000, LENGTH = 0x800
ram (rwx) : ORIGIN = 0x08000800, LENGTH = 0x1F800
flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x18000
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
/* The following regions define device specific memory regions and must not be changed. */
sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
SECTIONS
{
.cy_app_header :
{
KEEP(*(.cy_app_header))
} > flash
/* Cortex-M0+ application flash area */
.text :
{
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))
. = ALIGN(4);
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
/* Read-only code (constants). */
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.eh_frame*))
} > flash
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > flash
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > flash
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy interrupt vectors from flash to RAM */
LONG (__Vectors) /* From */
LONG (__ram_vectors_start__) /* To */
LONG (__Vectors_End - __Vectors) /* Size */
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG (__data_end__ - __data_start__) /* Size */
__copy_table_end__ = .;
} > flash
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm0plus.S */
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > flash
__etext = . ;
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
__StackLimit = __StackTop - STACK_SIZE ;
PROVIDE(__stack = __StackTop);
.stackSpace (NOLOAD) : ALIGN(8)
{
. = . + STACK_SIZE ;
} > ram
.ramVectors (NOLOAD) : ALIGN(8)
{
__ram_vectors_start__ = .;
KEEP(*(.ram_vectors))
__ram_vectors_end__ = .;
} > ram
/* Unprotected public RAM */
.cy_sharedmem (NOLOAD):
{
. = ALIGN(4);
__public_ram_start__ = .;
KEEP(*(.cy_sharedmem))
. = ALIGN(4);
__public_ram_end__ = .;
} > public_ram
.data __ram_vectors_end__ : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
KEEP(*(.cy_ramfunc*))
. = ALIGN(4);
__data_end__ = .;
} > ram
/* Place variables in the section that should not be initialized during the
* device startup.
*/
.noinit (NOLOAD) : ALIGN(8)
{
KEEP(*(.noinit))
} > ram
/* The uninitialized global or static variables are placed in this section.
*
* The NOLOAD attribute tells linker that .bss section does not consume
* any space in the image. The NOLOAD attribute changes the .bss type to
* NOBITS, and that makes linker to A) not allocate section in memory, and
* A) put information to clear the section with all zeros during application
* loading.
*
* Without the NOLOAD attribute, the .bss section might get PROGBITS type.
* This makes linker to A) allocate zeroed section in memory, and B) copy
* this section to RAM during application loading.
*/
.bss (NOLOAD):
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram
.heap (NOLOAD):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
. = ORIGIN(ram) + LENGTH(ram);
__HeapLimit = .;
} > ram
/* Emulated EEPROM Flash area */
.cy_em_eeprom :
{
KEEP(*(.cy_em_eeprom))
} > em_eeprom
/* Supervisory Flash: User data */
.cy_sflash_user_data :
{
KEEP(*(.cy_sflash_user_data))
} > sflash_user_data
/* Supervisory Flash: Normal Access Restrictions (NAR) */
.cy_sflash_nar :
{
KEEP(*(.cy_sflash_nar))
} > sflash_nar
/* Supervisory Flash: Public Key */
.cy_sflash_public_key :
{
KEEP(*(.cy_sflash_public_key))
} > sflash_public_key
/* Supervisory Flash: Table of Content # 2 */
.cy_toc_part2 :
{
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
/* Supervisory Flash: Table of Content # 2 Copy */
.cy_rtoc_part2 :
{
KEEP(*(.cy_rtoc_part2))
} > sflash_rtoc_2
/* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details.
*/
.cy_xip :
{
KEEP(*(.cy_xip))
} > xip
/* eFuse */
.cy_efuse :
{
KEEP(*(.cy_efuse))
} > efuse
/* These sections are used for additional metadata (silicon revision,
* Silicon/JTAG ID, etc.) storage.
*/
.cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
}
/* The following symbols used by the cymcuelftool. */
/* Flash */
__cy_memory_0_start = 0x10000000;
__cy_memory_0_length = 0x00200000;
__cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
__cy_memory_1_start = 0x14000000;
__cy_memory_1_length = 0x8000;
__cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
__cy_memory_2_start = 0x16000000;
__cy_memory_2_length = 0x8000;
__cy_memory_2_row_size = 0x200;
/* XIP */
__cy_memory_3_start = 0x18000000;
__cy_memory_3_length = 0x08000000;
__cy_memory_3_row_size = 0x200;
/* eFuse */
__cy_memory_4_start = 0x90700000;
__cy_memory_4_length = 0x100000;
__cy_memory_4_row_size = 1;
/* EOF */

113
bootloader/mcuboot/boot/cypress/MCUBootApp/MCUBootApp.mk Normal file
View File

@@ -0,0 +1,113 @@
################################################################################
# \file MCUBootApp.mk
# \version 1.0
#
# \brief
# Makefile for Cypress MCUBoot-based application.
#
################################################################################
# \copyright
# Copyright 2018-2019 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
################################################################################
include host.mk
# Cypress' MCUBoot Application supports GCC ARM only at this moment
# Set default compiler to GCC if not specified from command line
COMPILER ?= GCC_ARM
USE_CRYPTO_HW ?= 0
USE_EXTERNAL_FLASH ?= 0
MCUBOOT_IMAGE_NUMBER ?= 1
ENC_IMG ?= 0
# For which core this application is built
CORE ?= CM0P
ifneq ($(COMPILER), GCC_ARM)
$(error Only GCC ARM is supported at this moment)
endif
CUR_APP_PATH = $(PRJ_DIR)/$(APP_NAME)
include $(PRJ_DIR)/platforms.mk
include $(PRJ_DIR)/common_libs.mk
include $(PRJ_DIR)/toolchains.mk
# default slot size is 0x10000, 512bytes per row/sector, so 128 sectors
MAX_IMG_SECTORS ?= 128
# Application-specific DEFINES
DEFINES_APP := -DMBEDTLS_CONFIG_FILE="\"mcuboot_crypto_config.h\""
DEFINES_APP += -DECC256_KEY_FILE="\"keys/$(SIGN_KEY_FILE).pub\""
DEFINES_APP += -DCORE=$(CORE)
DEFINES_APP += -DMCUBOOT_IMAGE_NUMBER=$(MCUBOOT_IMAGE_NUMBER)
ifeq ($(USE_EXTERNAL_FLASH), 1)
DEFINES_APP += -DCY_BOOT_USE_EXTERNAL_FLASH
endif
DEFINES_APP += -DMCUBOOT_MAX_IMG_SECTORS=$(MAX_IMG_SECTORS)
# Hardrware acceleration support
ifeq ($(USE_CRYPTO_HW), 1)
DEFINES_APP += -DMBEDTLS_USER_CONFIG_FILE="\"mcuboot_crypto_acc_config.h\""
DEFINES_APP += -DCY_CRYPTO_HAL_DISABLE
DEFINES_APP += -DCY_MBEDTLS_HW_ACCELERATION
endif
# Encrypted image support
ifeq ($(ENC_IMG), 1)
DEFINES_APP += -DENC_IMG=1
endif
# Collect MCUBoot sourses
SOURCES_MCUBOOT := $(wildcard $(CURDIR)/../bootutil/src/*.c)
# Collect MCUBoot Application sources
SOURCES_APP_SRC := $(wildcard $(CUR_APP_PATH)/*.c)
# Collect Flash Layer port sources
SOURCES_FLASH_PORT := $(wildcard $(CURDIR)/cy_flash_pal/*.c)
SOURCES_FLASH_PORT += $(wildcard $(CURDIR)/cy_flash_pal/flash_qspi/*.c)
# Collect all the sources
SOURCES_APP := $(SOURCES_MCUBOOT)
SOURCES_APP += $(SOURCES_APP_SRC)
SOURCES_APP += $(SOURCES_FLASH_PORT)
INCLUDE_DIRS_MCUBOOT := $(addprefix -I, $(CURDIR)/../bootutil/include)
INCLUDE_DIRS_MCUBOOT += $(addprefix -I, $(CURDIR)/../bootutil/src)
INCLUDE_DIRS_MCUBOOT += $(addprefix -I, $(CURDIR)/..)
INCLUDE_DIRS_APP := $(addprefix -I, $(CURDIR))
INCLUDE_DIRS_APP += $(addprefix -I, $(CURDIR)/cy_flash_pal/flash_qspi)
INCLUDE_DIRS_APP += $(addprefix -I, $(CURDIR)/cy_flash_pal/include)
INCLUDE_DIRS_APP += $(addprefix -I, $(CURDIR)/cy_flash_pal/include/flash_map_backend)
INCLUDE_DIRS_APP += $(addprefix -I, $(CUR_APP_PATH))
INCLUDE_DIRS_APP += $(addprefix -I, $(CUR_APP_PATH)/config)
INCLUDE_DIRS_APP += $(addprefix -I, $(CUR_APP_PATH)/os)
ASM_FILES_APP :=
ASM_FILES_APP += $(ASM_FILES_STARTUP)
# Output folder
OUT := $(APP_NAME)/out
# Output folder to contain build artifacts
OUT_TARGET := $(OUT)/$(PLATFORM)
OUT_CFG := $(OUT_TARGET)/$(BUILDCFG)
# Overwite path to linker script if custom is required
ifeq ($(COMPILER), GCC_ARM)
LINKER_SCRIPT := $(subst /cygdrive/c,c:,$(CUR_APP_PATH)/$(APP_NAME).ld)
else
$(error Only GCC ARM is supported at this moment)
endif

62
bootloader/mcuboot/boot/cypress/MCUBootApp/MCUBootApp_CM0P_Debug.launch Normal file
View File

@@ -0,0 +1,62 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${cy_tools_path:openocd}/bin/openocd"/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-s &quot;${cy_tools_path:openocd}/scripts&quot;&#13;&#10;-s &quot;${workspace_loc}/boot/cypress&quot;&#13;&#10;-c &quot;source [find interface/kitprog3.cfg]&quot;&#13;&#10;-c &quot;source [find target/psoc6_2m.cfg]&quot;&#13;&#10;-c &quot;puts stderr {Started by GNU MCU Eclipse}&quot;"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="./out/PSOC_062_2M/Debug/MCUBootApp.elf"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="false"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value="./out/PSOC_062_2M/Debug/MCUBootApp.elf"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cy_sdk_install_dir}/tools/gcc-7.2.1-1.0/bin/arm-none-eabi-gdb${cy_exe_platform_ext}"/>
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="boot/cypress/MCUBootApp/out/PSOC_062_2M/Debug/MCUBootApp.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="cy_mcuboot"/>
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/cy_mcuboot"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;&gt;&#10;&lt;memoryBlockExpression address=&quot;268566528&quot; label=&quot;0x10020000&quot;/&gt;&#10;&lt;memoryBlockExpression address=&quot;268632064&quot; label=&quot;0x10030000&quot;/&gt;&#10;&lt;/memoryBlockExpressionList&gt;&#10;"/>
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
</launchConfiguration>

221
bootloader/mcuboot/boot/cypress/MCUBootApp/README.md Normal file
View File

@@ -0,0 +1,221 @@
### Port of MCUboot library to be used with Cypress targets
**Solution Description**
Given solution demonstrates operation of MCUboot on Cypress' PSoC6 device.
There are two applications implemented:
* MCUBootApp - PSoC6 MCUboot-based bootloading application;
* BlinkyApp - simple PSoC6 blinking LED application which is a target of BOOT/UPGRADE;
Cypress boards, that can be used with this evaluation example:
- CY8CPROTO-062-4343W - PSoC 6 2M on board
- CY8CKIT-062-WIFI-BT - PSoC 6 1M on board
- CY8CPROTO-062S3-4343W - PSoC 6 512K on board
The default flash map implemented is the following:
Single-image mode.
`[0x10000000, 0x10018000]` - MCUBootApp (bootloader) area;
`[0x10018000, 0x10028000]` - primary slot for BlinkyApp;
`[0x10028000, 0x10038000]` - secondary slot for BlinkyApp;
`[0x10038000, 0x10039000]` - scratch area (not used);
Size of slots `0x10000` - 64kb
MCUBootApp checks image integrity with SHA256, image authenticity with EC256 digital signature verification and uses completely SW implementation of cryptographic functions based on Mbed TLS Library.
**Important**: make sure primary, secondary slot and bootloader app sizes are appropriate and correspond to flash area size defined in Applications' linker files.
**Important**: make sure RAM areas of CM0p-based MCUBootApp bootloader and CM4-based BlinkyApp do not overlap.
Memory (stack) corruption of CM0p application can cause failure if SystemCall-served operations invoked from CM4.
### Hardware cryptography acceleration
Cypress PSOC6 MCU family supports hardware acceleration of cryptography based on Mbed TLS Library via shim layer. Implementation of this layer is supplied as separate submodule `cy-mbedtls-acceleration`. HW acceleration of cryptography shortens boot time more then 4 times, comparing to software implementation (observation results).
To enable hardware acceleration in `MCUBootApp` pass flag `USE_CRYPTO_HW=1` to `make` while build.
Hardware acceleration of cryptography is enabled for PSOC6 devices by default.
### How to modify memory map
__Option 1.__
Navigate to `sysflash.h` and modify the flash area(s) / slots sizes to meet your needs.
__Option 2.__
Navigate to `sysflash.h`, uncomment `CY_FLASH_MAP_EXT_DESC` definition.
Now define and initialize `struct flash_area *boot_area_descs[]` with flash memory addresses and sizes you need at the beginning of application, so flash APIs from `cy_flash_map.c` will use it.
__Note:__ for both options make sure you have updated `MCUBOOT_MAX_IMG_SECTORS` appropriatery with sector size assumed to be 512.
**How to override the flash map values during build process:**
Navigate to MCUBootApp.mk, find section `DEFINES_APP +=`
Update this line and or add similar for flash map parameters to override.
The possible list could be:
* MCUBOOT_MAX_IMG_SECTORS
* CY_FLASH_MAP_EXT_DESC
* CY_BOOT_SCRATCH_SIZE
* CY_BOOT_BOOTLOADER_SIZE
* CY_BOOT_PRIMARY_1_SIZE
* CY_BOOT_SECONDARY_1_SIZE
* CY_BOOT_PRIMARY_2_SIZE
* CY_BOOT_SECONDARY_2_SIZE
As an example in a makefile it should look like following:
`DEFINES_APP +=-DCY_FLASH_MAP_EXT_DESC`
`DEFINES_APP +=-DMCUBOOT_MAX_IMG_SECTORS=512`
`DEFINES_APP +=-DCY_BOOT_PRIMARY_1_SIZE=0x15000`
**Multi-Image Operation**
Multi-image operation considers upgrading and verification of more then one image on the device.
To enable multi-image operation define `MCUBOOT_IMAGE_NUMBER` in `MCUBootApp/config/mcuboot_config.h` file should be set to 2 (only dual-image is supported at the moment). This could also be done on build time by passing `MCUBOOT_IMAGE_NUMBER=2` as parameter to `make`.
Default value of `MCUBOOT_IMAGE_NUMBER` is 1, which corresponds to single image configuratios.
In multi-image operation (two images are considered for simplicity) MCUboot Bootloader application operates as following:
* Verifies Primary_1 and Primary_2 images;
* Verifies Secondary_1 and Secondary_2 images;
* Upgrades Secondary to Primary if valid images found;
* Boots image from Primary_1 slot only;
* Boots Primary_1 only if both - Primary_1 and Primary_2 are present and valid;
This ensures two dependent applications can be accepted by device only in case both images are valid.
**Default Flash map for Multi-Image operation:**
`0x10000000 - 0x10018000` - MCUboot Bootloader
`0x10018000 - 0x10028000` - Primary_1 (BOOT) slot of Bootloader
`0x10028000 - 0x10038000` - Secondary_1 (UPGRADE) slot of Bootloader
`0x10038000 - 0x10048000` - Primary_2 (BOOT) slot of Bootloader
`0x10048000 - 0x10058000` - Secondary_2 (UPGRADE) slot of Bootloader
`0x10058000 - 0x10059000` - Scratch of Bootloader
Size of slots `0x10000` - 64kb
__Note:__ It is also possible to place secondary (upgrade) slots in external memory module so resulting image size can be doubled.
For more details about External Memory usage, please refer to separate guiding document `ExternalMemory.md`.
### Hardware limitations
Since this application is created to demonstrate MCUboot library features and not as reference examples some considerations are taken.
1. `SCB5` used to configure serial port for debug prints. This is the most commonly used Serial Communication Block number among available Cypress PSoC 6 kits. If you try to use custom hardware with this application - change definition of `CYBSP_UART_HW` in `main.c` of MCUBootApp to SCB* that correspond to your design.
2. `CY_SMIF_SLAVE_SELECT_0` is used as definition SMIF driver API. This configuration is used on evaluation kit for this example CY8CPROTO-062-4343W, CY8PROTO-062S3-4343W, CY8CKIT-062-4343W. If you try to use custom hardware with this application - change value of `smif_id` in `main.c` of MCUBootApp to value that corresponds to your design.
### Downloading solution's assets
There is a set assets required:
* MCUBooot Library (root repository)
* PSoC6 HAL Library
* PSoC6 Peripheral Drivers Library (PDL)
* Mbed TLS Cryptographic Library
To get submodules - run the following command:
git submodule update --init --recursive
### Building solution
This folder contains make files infrastructure for building MCUBoot Bootloader. Same approach used in sample BlinkyLedApp application. Example command are provided below for couple different build configurations.
* Build MCUBootApp in `Debug` for signle image use case.
make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug MCUBOOT_IMAGE_NUMBER=1
* Build MCUBootApp in `Release` for multi image use case.
make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Release MCUBOOT_IMAGE_NUMBER=2
* To Build MCUBootApp with external memory support - pass `USE_EXTERNAL_FLASH=1` flag to `make` command in examples above. In this case UPGRADE image will be located in external memory. Refer to ExternalMemory.md for additional details.
Root directory for build is **boot/cypress.**
**Encrypted Image Support**
To protect user image from unwanted read - Upgrade Image Encryption can be applied. The ECDH/HKDF with EC256 scheme is used in a given solution as well as Mbed TLS as a crypto provider.
To enable image encryption support use `ENC_IMG=1` build flag (BlinkyApp should also be built with this flash set 1).
User is also responsible for providing corresponding binary key data in `enc_priv_key[]` (file `\MCUBootApp\keys.c`). The public part will be used by imgtool when signing and encrypting upgrade image. Signing image with encryption is described in `\BlinkyApp\Readme.md`.
After MCUBootApp is built with these settings unencrypted and encrypted images will be accepted in secondary (upgrade) slot.
Example command:
make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug MCUBOOT_IMAGE_NUMBER=1 ENC_IMG=1
**Programming solution**
There are couple ways of programming hex of MCUBootApp and BlinkyApp. Following instructions assume one of Cypress development kits, for example `CY8CPROTO_062_4343W`.
1. Direct usage of OpenOCD.
OpenOCD package is supplied with ModuToolbox IDE and can be found in installation folder under `./tools_2.1/openocd`.
Open terminal application - and execute following command after substitution `PATH_TO_APPLICATION.hex` and `OPENOCD` paths.
Connect a board to your computer. Switch Kitprog3 to DAP-BULK mode by pressing `SW3 MODE` button until `LED2 STATUS` constantly shines.
export OPENOCD=/Applications/ModusToolbox/tools_2.1/openocd
${OPENOCD}/bin/openocd -s ${OPENOCD}/scripts \
-f ${OPENOCD}/scripts/interface/kitprog3.cfg \
-f ${OPENOCD}/scripts/target/psoc6_2m.cfg \
-c "init; reset init; program PATH_TO_APPLICATION.hex" \
-c "resume; reset; exit"
2. Using GUI tool `Cypress Programmer` - follow [link](https://www.cypress.com/products/psoc-programming-solutions) to download.
Connect board to your computer. Switch Kitprog3 to DAP-BULK mode by pressing `SW3 MODE` button until `LED2 STATUS` constantly shines. Open `Cypress Programmer` and click `Connect`, then choose hex file: `MCUBootApp.hex` or `BlinkyApp.hex` and click `Program`. Check log to ensure programming success. Reset board.
3. Using `DAPLINK`.
Connect board to your computer. Switch embeded Kitprog3 to `DAPLINK` mode by pressing `SW3 MODE` button until `LED2 STATUS` blinks fast and mass storage device appeared in OS. Drag and drop `hex` files you wish to program to `DAPLINK` drive in your OS.
**Currently supported platforms:**
* PSOC_062_2M
* PSOC_062_1M
* PSOC_062_512K
**Build environment troubleshooting:**
Regular shell/terminal combination on Linux and MacOS.
On Windows:
* Cygwin
* Msys2
Also IDE may be used:
* Eclipse / ModusToolbox ("makefile project from existing source")
*Make* - make sure it is added to system's `PATH` variable and correct path is first in the list;
*Python/Python3* - make sure you have correct path referenced in `PATH`;
*Msys2* - to use systems PATH navigate to msys2 folder, open `msys2_shell.cmd`, uncomment set `MSYS2_PATH_TYPE=inherit`, restart MSYS2 shell.
This will iherit system's PATH so should find `python3.7` installed in regular way as well as imgtool and its dependencies.

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/*
* mcuboot_assert.h
*
* Cypress-specific assert() macro redefinition
*
*/
#ifndef MCUBOOT_ASSERT_H
#define MCUBOOT_ASSERT_H
//#include "cy_bootloader_services.h"
#define CYBL_ASSERT(...) Cy_BLServ_Assert(__VA_ARGS__)
#if !defined(NDEBUG)
#undef assert
#define assert(...) CYBL_ASSERT(__VA_ARGS__)
#else
#define assert
#endif
#endif /* MCUBOOT_ASSERT_H */

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/* Copyright 2019 Cypress Semiconductor Corporation
*
* Copyright (c) 2018 Open Source Foundries Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef MCUBOOT_CONFIG_H
#define MCUBOOT_CONFIG_H
/*
* Template configuration file for MCUboot.
*
* When porting MCUboot to a new target, copy it somewhere that your
* include path can find it as mcuboot_config/mcuboot_config.h, and
* make adjustments to suit your platform.
*
* For examples, see:
*
* boot/zephyr/include/mcuboot_config/mcuboot_config.h
* boot/mynewt/mcuboot_config/include/mcuboot_config/mcuboot_config.h
*/
/* Default maximum number of flash sectors per image slot; change
* as desirable. */
#ifndef MCUBOOT_MAX_IMG_SECTORS
#define MCUBOOT_MAX_IMG_SECTORS 2560
#endif
/*
* Signature types
*
* You must choose exactly one signature type.
*/
/* Uncomment for RSA signature support */
//#define MCUBOOT_SIGN_RSA
/* Uncomment for ECDSA signatures using curve P-256. */
#define MCUBOOT_SIGN_EC256
/*
* Upgrade mode
*
* The default is to support A/B image swapping with rollback. A
* simpler code path, which only supports overwriting the
* existing image with the update image, is also available.
*/
/* Uncomment to enable the overwrite-only code path. */
#define MCUBOOT_OVERWRITE_ONLY
#ifdef MCUBOOT_OVERWRITE_ONLY
/* Uncomment to only erase and overwrite those slot 0 sectors needed
* to install the new image, rather than the entire image slot. */
/* #define MCUBOOT_OVERWRITE_ONLY_FAST */
#endif
/*
* Cryptographic settings
*
* You must choose between mbedTLS and Tinycrypt as source of
* cryptographic primitives. Other cryptographic settings are also
* available.
*/
/* Uncomment to use ARM's mbedTLS cryptographic primitives */
#define MCUBOOT_USE_MBED_TLS
/* Uncomment to use Tinycrypt's. */
/* #define MCUBOOT_USE_TINYCRYPT */
/*
* Always check the signature of the image in slot 0 before booting,
* even if no upgrade was performed. This is recommended if the boot
* time penalty is acceptable.
*/
#define MCUBOOT_VALIDATE_PRIMARY_SLOT
/*
* Flash abstraction
*/
/* Uncomment if your flash map API supports flash_area_get_sectors().
* See the flash APIs for more details. */
// TODO: FWSECURITY-755
#define MCUBOOT_USE_FLASH_AREA_GET_SECTORS
/* Default number of separately updateable images; change in case of
* multiple images. */
#ifndef MCUBOOT_IMAGE_NUMBER
#define MCUBOOT_IMAGE_NUMBER 1
#endif
/*
* Currently there is no configuration option, for this platform,
* that enables the system specific mcumgr commands in mcuboot
*/
#define MCUBOOT_PERUSER_MGMT_GROUP_ENABLED 0
/*
* Logging
*/
/*
* If logging is enabled the following functions must be defined by the
* platform:
*
* MCUBOOT_LOG_ERR(...)
* MCUBOOT_LOG_WRN(...)
* MCUBOOT_LOG_INF(...)
* MCUBOOT_LOG_DBG(...)
*
* The following global logging level configuration macros must also be
* defined, each with a unique value. Those will be used to define a global
* configuration and will allow any source files to override the global
* configuration:
*
* MCUBOOT_LOG_LEVEL_OFF
* MCUBOOT_LOG_LEVEL_ERROR
* MCUBOOT_LOG_LEVEL_WARNING
* MCUBOOT_LOG_LEVEL_INFO
* MCUBOOT_LOG_LEVEL_DEBUG
*
* The global logging level must be defined, with one of the previously defined
* logging levels:
*
* #define MCUBOOT_LOG_LEVEL MCUBOOT_LOG_LEVEL_(OFF|ERROR|WARNING|INFO|DEBUG)
*
* MCUBOOT_LOG_LEVEL sets the minimum level that will be logged. The function
* priority is:
*
* MCUBOOT_LOG_ERR > MCUBOOT_LOG_WRN > MCUBOOT_LOG_INF > MCUBOOT_LOG_DBG
*
* NOTE: Each source file is still able to request its own logging level by
* defining BOOT_LOG_LEVEL before #including `bootutil_log.h`
*/
#define MCUBOOT_HAVE_LOGGING 1
/* Define this to support native mcuboot logging system */
#define CONFIG_MCUBOOT 1
/*
* Assertions
*/
/* Uncomment if your platform has its own mcuboot_config/mcuboot_assert.h.
* If so, it must provide an ASSERT macro for use by bootutil. Otherwise,
* "assert" is used. */
//#define MCUBOOT_HAVE_ASSERT_H
#define MCUBOOT_WATCHDOG_FEED() \
do { \
/* TODO: to be implemented */ \
} while (0)
/* Uncomment these if support of encrypted upgrade image is needed */
#ifdef ENC_IMG
#define MCUBOOT_ENC_IMAGES
#define MCUBOOT_ENCRYPT_EC256
#define NUM_ECC_BYTES (256 / 8)
#endif /* ENC_IMG */
/*
* No direct idle call implemented
*/
#define MCUBOOT_CPU_IDLE() \
do { \
} while (0)
#endif /* MCUBOOT_CONFIG_H */

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/*
* Copyright (c) 2018 Nordic Semiconductor ASA
* Copyright (c) 2015 Runtime Inc
* Copyright (c) 2020 Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
/*******************************************************************************/
#ifndef MCUBOOT_LOGGING_H
#define MCUBOOT_LOGGING_H
#include <stdio.h>
#define MCUBOOT_LOG_LEVEL_OFF 0
#define MCUBOOT_LOG_LEVEL_ERROR 1
#define MCUBOOT_LOG_LEVEL_WARNING 2
#define MCUBOOT_LOG_LEVEL_INFO 3
#define MCUBOOT_LOG_LEVEL_DEBUG 4
/*
* The compiled log level determines the maximum level that can be
* printed. Messages at or below this level can be printed, provided
* they are also enabled through the Rust logging system, such as by
* setting RUST_LOG to bootsim::api=info.
*/
#ifndef MCUBOOT_LOG_LEVEL
#define MCUBOOT_LOG_LEVEL MCUBOOT_LOG_LEVEL_INFO
#endif
int sim_log_enabled(int level);
#define sim_log_enabled(x) 1
#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_ERROR
#define MCUBOOT_LOG_ERR(_fmt, ...) \
do { \
if (sim_log_enabled(MCUBOOT_LOG_LEVEL_ERROR)) { \
fprintf(stderr, "[ERR] " _fmt "\n\r", ##__VA_ARGS__); \
} \
} while (0)
#else
#define MCUBOOT_LOG_ERR(...) IGNORE(__VA_ARGS__)
#endif
#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_WARNING
#define MCUBOOT_LOG_WRN(_fmt, ...) \
do { \
if (sim_log_enabled(MCUBOOT_LOG_LEVEL_WARNING)) { \
fprintf(stderr, "[WRN] " _fmt "\n\r", ##__VA_ARGS__); \
} \
} while (0)
#else
#define MCUBOOT_LOG_WRN(...) IGNORE(__VA_ARGS__)
#endif
#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_INFO
#define MCUBOOT_LOG_INF(_fmt, ...) \
do { \
if (sim_log_enabled(MCUBOOT_LOG_LEVEL_INFO)) { \
fprintf(stderr, "[INF] " _fmt "\n\r", ##__VA_ARGS__); \
} \
} while (0)
#else
#define MCUBOOT_LOG_INF(...) IGNORE(__VA_ARGS__)
#endif
#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_DEBUG
#define MCUBOOT_LOG_DBG(_fmt, ...) \
do { \
if (sim_log_enabled(MCUBOOT_LOG_LEVEL_DEBUG)) { \
fprintf(stderr, "[DBG] " _fmt "\n\r", ##__VA_ARGS__); \
} \
} while (0)
#else
#define MCUBOOT_LOG_DBG(...) IGNORE(__VA_ARGS__)
#endif
#define MCUBOOT_LOG_MODULE_DECLARE(...)
#endif /* MCUBOOT_LOGGING_H */

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/*
* mbed Microcontroller Library
* Copyright (c) 2019 Cypress Semiconductor Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* \file mcuboot_crypto_acc_config.h
* \version 1.1
*/
#ifndef MCUBOOT_MBEDTLS_DEVICE_H
#define MCUBOOT_MBEDTLS_DEVICE_H
/* Currently this target supports SHA1 */
// #define MBEDTLS_SHA1_C
#define MBEDTLS_SHA1_ALT
#define MBEDTLS_SHA256_ALT
#define MBEDTLS_SHA512_ALT
/* Currently this target supports CBC, CFB, OFB, CTR and XTS cipher modes */
#define MBEDTLS_AES_ALT
// #define MBEDTLS_CIPHER_MODE_CBC
// #define MBEDTLS_CIPHER_MODE_CFB
// #define MBEDTLS_CIPHER_MODE_OFB
#ifdef MCUBOOT_ENC_IMAGES
#define MBEDTLS_CIPHER_MODE_CTR
#endif
// #define MBEDTLS_CIPHER_MODE_XTS
/* Only NIST-P curves are currently supported */
#define MBEDTLS_ECP_ALT
// #define MBEDTLS_ECP_DP_SECP192R1_ENABLED
// #define MBEDTLS_ECP_DP_SECP224R1_ENABLED
// #define MBEDTLS_ECP_DP_SECP256R1_ENABLED
// #define MBEDTLS_ECP_DP_SECP384R1_ENABLED
// #define MBEDTLS_ECP_DP_SECP521R1_ENABLED
#define MBEDTLS_ECDSA_SIGN_ALT
#define MBEDTLS_ECDSA_VERIFY_ALT
#endif /* MCUBOOT_MBEDTLS_DEVICE_H */

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/*
* Copyright (c) 2020 Arm Limited.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "bootutil/security_cnt.h"
#include <stdint.h>
fih_ret
boot_nv_security_counter_init(void)
{
/* Do nothing. */
return FIH_SUCCESS;
}
fih_ret
boot_nv_security_counter_get(uint32_t image_id, fih_int *security_cnt)
{
(void)image_id;
*security_cnt = 30;
return FIH_SUCCESS;
}
int32_t
boot_nv_security_counter_update(uint32_t image_id, uint32_t img_security_cnt)
{
(void)image_id;
(void)img_security_cnt;
/* Do nothing. */
return 0;
}

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/***************************************************************************//**
* \file cy_serial_flash_prog.c
*
* \brief
* Provides variables necessary to inform programming tools how to program the
* attached serial flash memory. The variables used here must be placed at
* specific locations in order to be detected and used by programming tools
* to know that there is an attached memory and its characteristics. Uses the
* configuration provided as part of BSP.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_serial_flash Serial Flash
* \{
* Variables for informing programming tools that there is an attached memory device and what
* its characteristics are so it can be programmed just like the on-chip memory.
*
* \defgroup group_serial_flash_variables Variables
*/
#include <stdint.h>
#include "flash_qspi.h"
#if defined(__cplusplus)
extern "C" {
#endif
typedef struct
{
const cy_stc_smif_block_config_t * smifCfg; /* Pointer to SMIF top-level configuration */
const uint32_t null_t; /* NULL termination */
} stc_smif_ipblocks_arr_t;
/**
* \addtogroup group_serial_flash_variables
* \{
*/
/**
* This data can be placed anywhere in the internal memory, but it must be at a location that
* can be determined and used for the calculation of the CRC16 checksum in the cyToc below. There
* are multiple ways this can be accomplished including:
* 1) Placing it in a dedicated memory block with a known address. (as done here)
* 2) Placing it at an absolute location via a the linker script
* 3) Using 'cymcuelftool -S' to recompute the checksum and patch the elf file after linking
*/
CY_SECTION(".cy_sflash_user_data") __attribute__( (used) )
/* const stc_smif_ipblocks_arr_t smifIpBlocksArr = {&smifBlockConfig_sfdp, 0x00000000}; */
/* if used zero-pointer to config, DAP link will use hardcoded config for CY8CPROTO-062-4343W */
const stc_smif_ipblocks_arr_t smifIpBlocksArr = {0x00000000, 0x00000000};
/**
* This data is used to populate the table of contents part 2. When present, it is used by the boot
* process and programming tools to determine key characteristics about the memory usage including
* where the boot process should start the application from and what external memories are connected
* (if any). This must consume a full row of flash memory row. The last entry is a checksum of the
* other values in the ToC which must be updated if any other value changes. This can be done manually
* or by running 'cymcuelftool -S' to recompute the checksum.
*/
CY_SECTION(".cy_toc_part2") __attribute__( (used) )
const uint32_t cyToc[128] =
{
0x200-4, /* Offset=0x0000: Object Size, bytes */
0x01211220, /* Offset=0x0004: Magic Number (TOC Part 2, ID) */
0, /* Offset=0x0008: Key Storage Address */
(int)&smifIpBlocksArr, /* Offset=0x000C: This points to a null terminated array of SMIF structures. */
0x10000000u, /* Offset=0x0010: App image start address */
/* Offset=0x0014-0x01F7: Reserved */
[126] = 0x000002C2, /* Offset=0x01F8: Bits[ 1: 0] CLOCK_CONFIG (0=8MHz, 1=25MHz, 2=50MHz, 3=100MHz)
Bits[ 4: 2] LISTEN_WINDOW (0=20ms, 1=10ms, 2=1ms, 3=0ms, 4=100ms)
Bits[ 6: 5] SWJ_PINS_CTL (0/1/3=Disable SWJ, 2=Enable SWJ)
Bits[ 8: 7] APP_AUTHENTICATION (0/2/3=Enable, 1=Disable)
Bits[10: 9] FB_BOOTLOADER_CTL: UNUSED */
[127] = 0x3BB30000 /* Offset=0x01FC: CRC16-CCITT (the upper 2 bytes contain the CRC and the lower 2 bytes are 0) */
};
/** \} group_serial_flash_variables */
#if defined(__cplusplus)
}
#endif
/** \} group_serial_flash */

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/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
/*******************************************************************************
*
* This software is a port of the open source MCUBoot project.
*
* This file was modified to fit PSoC6-based MCUBoot applications.
*
* Portions of this software, including source code, documentation and related
* materials ("Software"), are owned by Cypress Semiconductor
* Corporation or one of its subsidiaries ("Cypress") and is protected by
* and subject to worldwide patent protection (United States and foreign),
* United States copyright laws and international treaty provisions.
* Therefore, you may use this Software only as provided in the license
* agreement accompanying the software package from which you
* obtained this Software ("EULA").
*
* If no EULA applies, Cypress hereby grants you a personal, non-
* exclusive, non-transferable license to copy, modify, and compile the
* Software source code solely for use in connection with Cypress's
* integrated circuit products. Any reproduction, modification, translation,
* compilation, or representation of this Software except as specified
* above is prohibited without the express written permission of Cypress.
*
* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO
* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING,
* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE. Cypress reserves the right to make
* changes to the Software without notice. Cypress does not assume any
* liability arising out of the application or use of the Software or any
* product or circuit described in the Software. Cypress does not
* authorize its products for use in any products where a malfunction or
* failure of the Cypress product may reasonably be expected to result in
* significant property damage, injury or death ("High Risk Product"). By
* including Cypress's product in a High Risk Product, the manufacturer
* of such system or application assumes all risk of such use and in doing
* so agrees to indemnify Cypress against all liability.
*
********************************************************************************/
#include <bootutil/sign_key.h>
#include <mcuboot_config/mcuboot_config.h>
#if !defined(MCUBOOT_HW_KEY)
#if defined(MCUBOOT_SIGN_RSA)
const unsigned char rsa_pub_key[] = {
0x30, 0x82, 0x01, 0x0a, 0x02, 0x82, 0x01, 0x01, 0x00, 0xd1, 0x06, 0x08,
0x1a, 0x18, 0x44, 0x2c, 0x18, 0xe8, 0xfb, 0xfd, 0xf7, 0x0d, 0xa3, 0x4f,
0x1f, 0xbb, 0xee, 0x5e, 0xf9, 0xaa, 0xd2, 0x4b, 0x18, 0xd3, 0x5a, 0xe9,
0x6d, 0x18, 0x80, 0x19, 0xf9, 0xf0, 0x9c, 0x34, 0x1b, 0xcb, 0xf3, 0xbc,
0x74, 0xdb, 0x42, 0xe7, 0x8c, 0x7f, 0x10, 0x53, 0x7e, 0x43, 0x5e, 0x0d,
0x57, 0x2c, 0x44, 0xd1, 0x67, 0x08, 0x0f, 0x0d, 0xbb, 0x5c, 0xee, 0xec,
0xb3, 0x99, 0xdf, 0xe0, 0x4d, 0x84, 0x0b, 0xaa, 0x77, 0x41, 0x60, 0xed,
0x15, 0x28, 0x49, 0xa7, 0x01, 0xb4, 0x3c, 0x10, 0xe6, 0x69, 0x8c, 0x2f,
0x5f, 0xac, 0x41, 0x4d, 0x9e, 0x5c, 0x14, 0xdf, 0xf2, 0xf8, 0xcf, 0x3d,
0x1e, 0x6f, 0xe7, 0x5b, 0xba, 0xb4, 0xa9, 0xc8, 0x88, 0x7e, 0x47, 0x3c,
0x94, 0xc3, 0x77, 0x67, 0x54, 0x4b, 0xaa, 0x8d, 0x38, 0x35, 0xca, 0x62,
0x61, 0x7e, 0xb7, 0xe1, 0x15, 0xdb, 0x77, 0x73, 0xd4, 0xbe, 0x7b, 0x72,
0x21, 0x89, 0x69, 0x24, 0xfb, 0xf8, 0x65, 0x6e, 0x64, 0x3e, 0xc8, 0x0e,
0xd7, 0x85, 0xd5, 0x5c, 0x4a, 0xe4, 0x53, 0x0d, 0x2f, 0xff, 0xb7, 0xfd,
0xf3, 0x13, 0x39, 0x83, 0x3f, 0xa3, 0xae, 0xd2, 0x0f, 0xa7, 0x6a, 0x9d,
0xf9, 0xfe, 0xb8, 0xce, 0xfa, 0x2a, 0xbe, 0xaf, 0xb8, 0xe0, 0xfa, 0x82,
0x37, 0x54, 0xf4, 0x3e, 0xe1, 0x2b, 0xd0, 0xd3, 0x08, 0x58, 0x18, 0xf6,
0x5e, 0x4c, 0xc8, 0x88, 0x81, 0x31, 0xad, 0x5f, 0xb0, 0x82, 0x17, 0xf2,
0x8a, 0x69, 0x27, 0x23, 0xf3, 0xab, 0x87, 0x3e, 0x93, 0x1a, 0x1d, 0xfe,
0xe8, 0xf8, 0x1a, 0x24, 0x66, 0x59, 0xf8, 0x1c, 0xab, 0xdc, 0xce, 0x68,
0x1b, 0x66, 0x64, 0x35, 0xec, 0xfa, 0x0d, 0x11, 0x9d, 0xaf, 0x5c, 0x3a,
0xa7, 0xd1, 0x67, 0xc6, 0x47, 0xef, 0xb1, 0x4b, 0x2c, 0x62, 0xe1, 0xd1,
0xc9, 0x02, 0x03, 0x01, 0x00, 0x01
};
const unsigned int rsa_pub_key_len = 270;
#elif defined(MCUBOOT_SIGN_EC256)
/* Format of PEM :
* -----BEGIN PUBLIC KEY-----
* base64encode(DER)
* -----END PUBLIC KEY----- */
#if defined(ECC256_KEY_FILE)
#include ECC256_KEY_FILE
#else
#warning "Used default ECC256 ecdsa_pub_key"
/* It is OEM_PUB_KEY at this moment for debug purposes */
const unsigned char ecdsa_pub_key[] = {
0x30, 0x59, 0x30, 0x13, 0x06, 0x07, 0x2a, 0x86,
0x48, 0xce, 0x3d, 0x02, 0x01, 0x06, 0x08, 0x2a,
0x86, 0x48, 0xce, 0x3d, 0x03, 0x01, 0x07, 0x03,
0x42, 0x00, 0x04, 0xbd, 0x59, 0x9d, 0x15, 0xe0,
0xff, 0x66, 0x12, 0x37, 0x28, 0xdf, 0x50, 0x38,
0xb1, 0x9a, 0x73, 0x9b, 0xbd, 0xd1, 0xb3, 0x8a,
0x6f, 0xd2, 0x70, 0xed, 0x7f, 0xdb, 0x57, 0x53,
0xde, 0x9e, 0x77, 0x0f, 0x9c, 0x17, 0x22, 0x69,
0xa6, 0x75, 0x48, 0x1f, 0xa4, 0xbc, 0x49, 0xe2,
0x01, 0xe0, 0x5e, 0x3d, 0xec, 0xa8, 0xc1, 0xca,
0xc5, 0x5c, 0xa2, 0xc6, 0xfd, 0xb0, 0x24, 0xb1,
0x0a, 0x46, 0xf5,
};
const unsigned int ecdsa_pub_key_len = 91;
#endif
#else
#warning "No public key available for given signing algorithm."
#endif
#if defined(MCUBOOT_SIGN_RSA) || \
defined(MCUBOOT_SIGN_EC256)
const struct bootutil_key bootutil_keys[] = {
#if defined(MCUBOOT_SIGN_RSA)
{
.key = rsa_pub_key,
.len = &rsa_pub_key_len,
},
#elif defined(MCUBOOT_SIGN_EC256)
{
.key = ecdsa_pub_key,
.len = &ecdsa_pub_key_len,
},
#else
{
.key = NULL,
.len = 0x00,
},
#endif
};
const int bootutil_key_cnt = 1;
#endif
#else
unsigned int pub_key_len;
struct bootutil_key bootutil_keys[1] = {
{
.key = 0,
.len = &pub_key_len,
}
};
const int bootutil_key_cnt = 1;
#endif /* !MCUBOOT_HW_KEY */
unsigned char enc_priv_key[] = {
0x30, 0x81, 0x87, 0x02, 0x01, 0x00, 0x30, 0x13, 0x06, 0x07, 0x2a, 0x86,
0x48, 0xce, 0x3d, 0x02, 0x01, 0x06, 0x08, 0x2a, 0x86, 0x48, 0xce, 0x3d,
0x03, 0x01, 0x07, 0x04, 0x6d, 0x30, 0x6b, 0x02, 0x01, 0x01, 0x04, 0x20,
0xf6, 0x1e, 0x51, 0x9d, 0xf8, 0xfa, 0xdd, 0xa1, 0xb7, 0xd9, 0xa9, 0x64,
0x64, 0x3b, 0x54, 0xd0, 0x3d, 0xd0, 0x1f, 0xe5, 0x78, 0xd9, 0x17, 0x98,
0xa5, 0x28, 0xca, 0xcc, 0x6b, 0x67, 0x9e, 0x06, 0xa1, 0x44, 0x03, 0x42,
0x00, 0x04, 0x8a, 0x44, 0x73, 0x00, 0x94, 0xc9, 0x80, 0x27, 0x31, 0x0d,
0x23, 0x36, 0x6b, 0xe9, 0x69, 0x9f, 0xcb, 0xc5, 0x7c, 0xc8, 0x44, 0x1a,
0x93, 0xe6, 0xee, 0x7d, 0x86, 0xa6, 0xae, 0x5e, 0x93, 0x72, 0x74, 0xd9,
0xe1, 0x5a, 0x1c, 0x9b, 0x65, 0x1a, 0x2b, 0x61, 0x41, 0x28, 0x02, 0x73,
0x84, 0x12, 0x97, 0x3a, 0x2d, 0xa2, 0xa0, 0x67, 0x77, 0x02, 0xda, 0x67,
0x1a, 0x4b, 0xdd, 0xd7, 0x71, 0xcc,
};
static unsigned int enc_priv_key_len = 138;
const struct bootutil_key bootutil_enc_key = {
.key = enc_priv_key,
.len = &enc_priv_key_len,
};

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################################################################################
# \file libs.mk
# \version 1.0
#
# \brief
# Makefile to describe libraries needed for Cypress MCUBoot based applications.
#
################################################################################
# \copyright
# Copyright 2018-2019 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
################################################################################
################################################################################
# PDL library
################################################################################
PDL_VERSION = 121
THIS_APP_PATH = $(PRJ_DIR)/libs
MBEDTLS_PATH = $(PRJ_DIR)/../../ext
# Add platform folder to build
SOURCES_PLATFORM += $(wildcard $(PRJ_DIR)/platforms/*.c)
SOURCES_WATCHDOG := $(wildcard $(THIS_APP_PATH)/watchdog/*.c)
# Add retartget IO implementation using pdl
SOURCES_RETARGET_IO_PDL += $(wildcard $(THIS_APP_PATH)/retarget_io_pdl/*.c)
# Collect dirrectories containing headers for PLATFORM
INCLUDE_RETARGET_IO_PDL += $(THIS_APP_PATH)/retarget_io_pdl
# PSOC6HAL source files
SOURCES_HAL += $(THIS_APP_PATH)/psoc6hal/COMPONENT_PSOC6HAL/source/cyhal_crypto_common.c
SOURCES_HAL += $(THIS_APP_PATH)/psoc6hal/COMPONENT_PSOC6HAL/source/cyhal_hwmgr.c
# MbedTLS source files
SOURCES_MBEDTLS := $(wildcard $(MBEDTLS_PATH)/mbedtls/library/*.c)
# Collected source files for libraries
SOURCES_LIBS += $(SOURCES_HAL)
SOURCES_LIBS += $(SOURCES_MBEDTLS)
SOURCES_LIBS += $(SOURCES_WATCHDOG)
SOURCES_LIBS += $(SOURCES_PLATFORM)
SOURCES_LIBS += $(SOURCES_RETARGET_IO_PDL)
# Include platforms folder
INCLUDE_DIRS_PLATFORM := $(PRJ_DIR)/platforms
# needed for Crypto HW Acceleration and headers inclusion, do not use for peripherals
# peripherals should be accessed
INCLUDE_DIRS_HAL := $(THIS_APP_PATH)/psoc6hal/COMPONENT_PSOC6HAL/include
INCLUDE_DIRS_HAL += $(THIS_APP_PATH)/psoc6hal/include
INCLUDE_DIRS_HAL += $(THIS_APP_PATH)/psoc6hal/COMPONENT_PSOC6HAL/include/pin_packages
# MbedTLS related include directories
INCLUDE_DIRS_MBEDTLS += $(MBEDTLS_PATH)/mbedtls/include
INCLUDE_DIRS_MBEDTLS += $(MBEDTLS_PATH)/mbedtls/include/mbedtls
INCLUDE_DIRS_MBEDTLS += $(MBEDTLS_PATH)/mbedtls/include/psa
INCLUDE_DIRS_MBEDTLS += $(MBEDTLS_PATH)/mbedtls/library
# Watchdog related includes
INCLUDE_DIRS_WATCHDOG := $(THIS_APP_PATH)/watchdog
# Collected include directories for libraries
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_HAL))
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_WATCHDOG))
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_MBEDTLS))
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_RETARGET_IO_PDL))
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_PLATFORM))
################################################################################
# mbedTLS hardware acceleration settings
################################################################################
ifeq ($(USE_CRYPTO_HW), 1)
# cy-mbedtls-acceleration related include directories
INCLUDE_DIRS_MBEDTLS_MXCRYPTO := $(THIS_APP_PATH)/cy-mbedtls-acceleration/mbedtls_MXCRYPTO
# Collect source files for MbedTLS acceleration
SOURCES_MBEDTLS_MXCRYPTO := $(wildcard $(THIS_APP_PATH)/cy-mbedtls-acceleration/mbedtls_MXCRYPTO/*.c)
#
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_MBEDTLS_MXCRYPTO))
# Collected source files for libraries
SOURCES_LIBS += $(SOURCES_MBEDTLS_MXCRYPTO)
endif

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/***************************************************************************//**
* \file main.c
* \version 1.0
********************************************************************************
* \copyright
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/* Cypress pdl headers */
#include "cy_pdl.h"
#include "cy_retarget_io_pdl.h"
#include "cy_result.h"
#include "cycfg_clocks.h"
#include "cycfg_peripherals.h"
#include "cycfg_pins.h"
#include "flash_qspi.h"
#include "sysflash/sysflash.h"
#include "flash_map_backend/flash_map_backend.h"
#include "bootutil/image.h"
#include "bootutil/bootutil.h"
#include "bootutil/sign_key.h"
#include "bootutil/bootutil_log.h"
#include "bootutil/fault_injection_hardening.h"
#include "watchdog.h"
/* WDT time out for reset mode, in milliseconds. */
#define WDT_TIME_OUT_MS 4000
/* Define pins for UART debug output */
#define CYBSP_UART_ENABLED 1U
#define CYBSP_UART_HW SCB5
#define CYBSP_UART_IRQ scb_5_interrupt_IRQn
#ifdef CY_BOOT_USE_EXTERNAL_FLASH
/* Choose SMIF slot number (slave select).
* Acceptable values are:
* 0 - SMIF disabled (no external memory);
* 1, 2, 3 or 4 - slave select line memory module is connected to.
*/
uint32_t smif_id = 1; /* Assume SlaveSelect_0 is used for External Memory */
#endif
void hw_deinit(void);
static void do_boot(struct boot_rsp *rsp)
{
uint32_t app_addr = 0;
app_addr = (rsp->br_image_off + rsp->br_hdr->ih_hdr_size);
BOOT_LOG_INF("Starting User Application on CM4 (wait)...");
BOOT_LOG_INF("Start Address: 0x%08lx", app_addr);
BOOT_LOG_INF("Deinitializing hardware...");
cy_retarget_io_wait_tx_complete(CYBSP_UART_HW, 10);
hw_deinit();
Cy_SysEnableCM4(app_addr);
}
int main(void)
{
struct boot_rsp rsp;
cy_rslt_t rc = CY_RSLT_TYPE_ERROR;
bool boot_succeeded = false;
FIH_DECLARE(fih_rc, FIH_FAILURE);
SystemInit();
//init_cycfg_clocks();
init_cycfg_peripherals();
init_cycfg_pins();
/* Certain PSoC 6 devices enable CM4 by default at startup. It must be
* either disabled or enabled & running a valid application for flash write
* to work from CM0+. Since flash write may happen in boot_go() for updating
* the image before this bootloader app can enable CM4 in do_boot(), we need
* to keep CM4 disabled. Note that debugging of CM4 is not supported when it
* is disabled.
*/
#if defined(CY_DEVICE_PSOC6ABLE2)
if (CY_SYS_CM4_STATUS_ENABLED == Cy_SysGetCM4Status())
{
Cy_SysDisableCM4();
}
#endif /* #if defined(CY_DEVICE_PSOC6ABLE2) */
/* enable interrupts */
__enable_irq();
/* Initialize retarget-io to use the debug UART port (CYBSP_UART_HW) */
rc = cy_retarget_io_pdl_init(115200u);
if (rc != CY_RSLT_SUCCESS)
{
CY_ASSERT(0);
}
BOOT_LOG_INF("MCUBoot Bootloader Started");
#ifdef CY_BOOT_USE_EXTERNAL_FLASH
rc = CY_SMIF_CMD_NOT_FOUND;
#undef MCUBOOT_MAX_IMG_SECTORS
/* redefine number of sectors as there 2MB will be
* available on PSoC062-2M in case of external
* memory usage */
#define MCUBOOT_MAX_IMG_SECTORS 4096
rc = qspi_init_sfdp(smif_id);
if (rc == CY_SMIF_SUCCESS)
{
BOOT_LOG_INF("External Memory initialized w/ SFDP.");
}
else
{
BOOT_LOG_ERR("External Memory initialization w/ SFDP FAILED: 0x%02x", (int)rc);
}
if (CY_SMIF_SUCCESS == rc)
#endif
{
FIH_CALL(boot_go, fih_rc, &rsp);
if (FIH_EQ(fih_rc, FIH_SUCCESS))
{
BOOT_LOG_INF("User Application validated successfully");
/* initialize watchdog timer. it should be updated from user app
* to mark successful start up of this app. if the watchdog is not updated,
* reset will be initiated by watchdog timer and swap revert operation started
* to roll back to operable image.
*/
cy_wdg_init(WDT_TIME_OUT_MS);
do_boot(&rsp);
boot_succeeded = true;
}
else
{
BOOT_LOG_INF("MCUBoot Bootloader found none of bootable images");
}
}
while (1)
{
if (boot_succeeded) {
Cy_SysPm_CpuEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT);
}
else {
__WFI();
}
}
return 0;
}
void hw_deinit(void)
{
cy_retarget_io_pdl_deinit();
Cy_GPIO_Port_Deinit(CYBSP_UART_RX_PORT);
Cy_GPIO_Port_Deinit(CYBSP_UART_TX_PORT);
#ifdef CY_BOOT_USE_EXTERNAL_FLASH
qspi_deinit(smif_id);
#endif
}

18
bootloader/mcuboot/boot/cypress/MCUBootApp/os/os.h Normal file
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/***************************************************************************//**
* \file os.h
* \version 1.0
*
* \brief
* Objective:
* Heap init prototype
*
********************************************************************************
* \copyright
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
void os_heap_init(void);

37
bootloader/mcuboot/boot/cypress/MCUBootApp/os/os_heap.h Normal file
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/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
#ifndef H_OS_HEAP_
#define H_OS_HEAP_
#include <stddef.h>
#ifdef __cplusplus
extern "C" {
#endif
void *os_malloc(size_t size);
void os_free(void *mem);
void *os_realloc(void *ptr, size_t size);
#ifdef __cplusplus
}
#endif
#endif

42
bootloader/mcuboot/boot/cypress/MCUBootApp/os/os_malloc.h Normal file
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/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
#ifndef H_OS_MALLOC_
#define H_OS_MALLOC_
#include "os/os_heap.h"
#ifdef __cplusplus
extern "C" {
#endif
#undef malloc
#define malloc os_malloc
#undef free
#define free os_free
#undef realloc
#define realloc os_realloc
#ifdef __cplusplus
}
#endif
#endif

81
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/* Manual version of auto-generated version. */
#ifndef __SYSFLASH_H__
#define __SYSFLASH_H__
#define FLASH_DEVICE_INTERNAL_FLASH (0x7F)
#define FLASH_AREA_BOOTLOADER 0
#define FLASH_AREA_IMAGE_0 1
#define FLASH_AREA_IMAGE_1 2
#define FLASH_AREA_IMAGE_SCRATCH 3
#define FLASH_AREA_IMAGE_2 5
#define FLASH_AREA_IMAGE_3 6
/* Uncomment if external flash is being used */
/* #define CY_BOOT_USE_EXTERNAL_FLASH */
/* use PDL-defined offset or one from SMFI config */
#define CY_SMIF_BASE_MEM_OFFSET (0x18000000)
#define CY_FLASH_ALIGN (CY_FLASH_SIZEOF_ROW)
#define CY_FLASH_DEVICE_BASE (CY_FLASH_BASE)
#ifndef CY_BOOT_SCRATCH_SIZE
#define CY_BOOT_SCRATCH_SIZE (0x1000)
#endif
#ifndef CY_BOOT_BOOTLOADER_SIZE
#define CY_BOOT_BOOTLOADER_SIZE (0x18000)
#endif
#ifndef CY_BOOT_PRIMARY_1_SIZE
#define CY_BOOT_PRIMARY_1_SIZE (0x10000)
#endif
#ifndef CY_BOOT_SECONDARY_1_SIZE
#define CY_BOOT_SECONDARY_1_SIZE (0x10000)
#endif
#if (MCUBOOT_IMAGE_NUMBER == 2) /* if dual-image */
#ifndef CY_BOOT_PRIMARY_2_SIZE
#define CY_BOOT_PRIMARY_2_SIZE (0x10000)
#endif
#ifndef CY_BOOT_SECONDARY_2_SIZE
#define CY_BOOT_SECONDARY_2_SIZE (0x10000)
#endif
#endif
#if (MCUBOOT_IMAGE_NUMBER == 1)
#define FLASH_AREA_IMAGE_PRIMARY(x) (((x) == 0) ? \
FLASH_AREA_IMAGE_0 : \
FLASH_AREA_IMAGE_0)
#define FLASH_AREA_IMAGE_SECONDARY(x) (((x) == 0) ? \
FLASH_AREA_IMAGE_1 : \
FLASH_AREA_IMAGE_1)
#elif (MCUBOOT_IMAGE_NUMBER == 2)
#define FLASH_AREA_IMAGE_PRIMARY(x) (((x) == 0) ? \
FLASH_AREA_IMAGE_0 : \
((x) == 1) ? \
FLASH_AREA_IMAGE_2 : \
255)
#define FLASH_AREA_IMAGE_SECONDARY(x) (((x) == 0) ? \
FLASH_AREA_IMAGE_1 : \
((x) == 1) ? \
FLASH_AREA_IMAGE_3 : \
255)
#else
#warning "Image slot and flash area mapping is not defined"
#endif
#define CY_IMG_HDR_SIZE 0x400
#ifndef CY_FLASH_MAP_EXT_DESC
/* Uncomment in case you want to use separately defined table of flash area descriptors */
/* #define CY_FLASH_MAP_EXT_DESC */
#endif
#endif /* __SYSFLASH_H__ */

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################################################################################
# \file Makefile
# \version 1.0
#
# \brief
# Main Makefile for building MCUBoot application for Cypress target.
#
################################################################################
# \copyright
# Copyright 2018-2021 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
################################################################################
# minimum Python 3.7 is required
# Python path definition
ifeq ($(OS),Windows_NT)
PYTHON_PATH?=python
else
PYTHON_PATH?=python3
endif
################################################################################
# Main settings
################################################################################
# Defines whether or not show verbose build output
MAKEINFO ?= 1
# Application name by default
APP_NAME ?= MCUBootApp
# Weather or now execute post build script after build - set to 0 for CI
POST_BUILD ?= 1
SIGN_KEY_FILE ?= cypress-test-ec-p256
ENC_KEY_FILE ?= enc-ec256-pub
ENC_IMG ?= 0
# set this variable to a path, where cysecuretools python package is installed
# use command `python -m pip show cysecuretools` to find out this path
# or rely on scripts that automates this action, bit not work for virtual envs
CY_SEC_TOOLS_PATH ?= $(shell $(PYTHON_PATH) $(CURDIR)/scripts/find_cysectools.py)
BUILDCFG ?= Debug
# Set of supported applications
APPS := MCUBootApp BlinkyApp
HEADER_OFFSET ?= 0
ifneq ($(filter $(APP_NAME), $(APPS)),)
include ./$(APP_NAME)/$(APP_NAME).mk
include ./$(APP_NAME)/libs.mk
else
$(error Not supported application: '$(APP_NAME)')
endif
ASM_FILES := $(ASM_FILES_APP)
ASM_FILES += $(ASM_FILES_LIBS)
C_FILES := $(SOURCES_APP)
C_FILES += $(SOURCES_LIBS)
INCLUDE_DIRS := $(INCLUDE_DIRS_APP)
INCLUDE_DIRS += $(INCLUDE_DIRS_MCUBOOT)
INCLUDE_DIRS += $(INCLUDE_DIRS_LIBS)
#INCLUDE_FILES := $(INCLUDE_FILES_APP)
#INCLUDES := $(addprefix -include , $(INCLUDE_FILES))
O_FILES := $(notdir $(C_FILES:.c=.o)) $(addsuffix .o, $(notdir $(basename $(ASM_FILES))))
DEFINES := $(DEFINES_APP)
DEFINES += $(DEFINES_LIBS)
AS_FLAGS += $(DEFINES)
ifeq ($(MAKEINFO), 1)
$(info ==============================================================================)
$(info = Directories to look for header files: =)
$(info ==============================================================================)
$(info $(INCLUDE_DIRS))
$(info ==============================================================================)
$(info = Collected Defines string: =)
$(info ==============================================================================)
$(info $(DEFINES))
endif
# updating CFLAGS at this point as DEFINES are completed
CFLAGS += $(DEFINES)
VPATH = $(dir $(C_FILES) $(ASM_FILES))
#
# STDE: For cygwin, adjust paths for compiler
#
MY_FILES := $(subst /cygdrive/c,c:,$(C_FILES))
#$(info MY_FILES $(MY_FILES))
C_FILES=$(MY_FILES)
MY_DIRS := $(subst /cygdrive/c,c:,$(INCLUDE_DIRS))
#$(info MY_DIRS $(MY_DIRS))
INCLUDE_DIRS=$(MY_DIRS)
MY_ASM_FILES := $(subst /cygdrive/c,c:,$(ASM_FILES))
#$(info MY_ASM_FILES $(MY_ASM_FILES))
ASM_FILES=$(MY_ASM_FILES)
MY_LDFLAGS := $(subst /cygdrive/c,c:,$(LDFLAGS))
#$(info MY_LDFLAGS $(MY_LDFLAGS))
LDFLAGS=$(MY_LDFLAGS)
# Default name pattern for output files
# may be modified in %Application%.mk file
OUT_FILE_NAME ?= $(OUT_APP)/$(APP_NAME)
OUT_OBJ := $(OUT_CFG)/obj
OUT_APP := $(OUT_CFG)
.PHONY: all app build clean pre_build post_build
all: clean app
app:
@`mkdir -p ./$(OUT)`
@`mkdir -p ./$(OUT_TARGET)`
@`mkdir -p ./$(OUT_CFG)`
@`mkdir -p ./$(OUT_OBJ)`
$(MAKE) pre_build
$(MAKE) build -j8
$(MAKE) post_build
build: $(OUT_APP)/$(APP_NAME).hex
$(GCC_PATH)/bin/arm-none-eabi-objdump $(OUT_APP)/$(APP_NAME).elf -S --disassemble > $(OUT_APP)/$(APP_NAME).lst
$(GCC_PATH)/bin/arm-none-eabi-objdump -h $(OUT_APP)/$(APP_NAME).elf
$(GCC_PATH)/bin/arm-none-eabi-size --format=SysV $(OUT_APP)/$(APP_NAME).elf
$(OUT_APP)/$(APP_NAME).hex: $(OUT_APP)/$(APP_NAME).elf
$(GCC_PATH)/bin/arm-none-eabi-objcopy --change-addresses=$(HEADER_OFFSET) -O ihex $(OUT_APP)/$(APP_NAME).elf $(OUT_APP)/$(APP_NAME).hex
$(OUT_APP)/$(APP_NAME).elf: $(addprefix $(OUT_OBJ)/, $(O_FILES))
@echo "LD $@"
ifeq ($(MAKEINFO), 1)
@echo $(LD) $(O_FILES) $(CC_DEPEND) $(@:.o=.d) -o $@ $(LDFLAGS) -T $(LINKER_SCRIPT) -Wl,-Map,$(OUT_FILE_NAME).map
endif
@$(LD) $(addprefix $(OUT_OBJ)/, $(O_FILES)) $(CC_DEPEND) $(@:.o=.d) -o $@ $(LDFLAGS) -T $(LINKER_SCRIPT) -Wl,-Map,$(OUT_FILE_NAME).map
$(OUT_OBJ)/%.o: %.c
@echo "CC $<"
ifeq ($(MAKEINFO), 1)
@echo $(CC) $(CFLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
endif
@$(CC) $(CFLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
ifeq ($(MAKEINFO), 1)
@echo
endif
$(OUT_OBJ)/%.o: %.S
@echo "AS $<"
ifeq ($(COMPILER), GCC_ARM)
ifeq ($(MAKEINFO), 1)
@echo @$(CC) $(CFLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
endif
@$(CC) $(CFLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
else
@echo $(AS) $< -o $@ $(AS_FLAGS)
@$(AS) $< -o $@ $(AS_FLAGS)
endif
ifeq ($(MAKEINFO), 1)
@echo
endif
clean:
@echo "Cleanup out directory..."
rm -rf $(OUT_TARGET)/$(BUILDCFG)
clean_boot:
@echo "Cleanup out BOOT directory of $(APP_NAME)..."
rm -rf $(OUT_TARGET)/$(BUILDCFG)/boot
clean_upgrade:
@echo "Cleanup out UPGRADE directory of $(APP_NAME)..."
rm -rf $(OUT_TARGET)/$(BUILDCFG)/upgrade
run_cppcheck:
@echo "Performing static code analysis with Cppcheck tool..."
cppcheck/cppcheck.sh $(APP_NAME) $(PLATFORM) "$(DEFINES)" "$(INCLUDE_DIRS)" "$(C_FILES)" $(CPP_CHECK_SCOPE) $(BUILDCFG)
gen_key_ecc256:
@echo Generate ECC256 keys: $(SIGN_KEY_FILE).pem and $(SIGN_KEY_FILE).pub
../../scripts/imgtool.py keygen -k keys/$(SIGN_KEY_FILE).pem -t ecdsa-p256
../../scripts/imgtool.py getpub -k keys/$(SIGN_KEY_FILE).pem > keys/$(SIGN_KEY_FILE).pub
ifeq ($(MAKEINFO) , 1)
$(info ASM_FILES: $(ASM_FILES))
$(info C_FILES: $(C_FILES))
$(info INCLUDE_DIRS: $(INCLUDE_DIRS))
$(info DEFINES: $(DEFINES))
$(info CC: $(CC))
endif

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### Port of MCUBoot library for evaluation with Cypress PSoC 6 chips
### Disclaimer
Given solution is included in `MCUboot` repository with purpose to demonstrate basic consepts and features of MCUboot library on Cypress PSoC 6 device. Applications are created per MCUboot library maintainers requirements. Implemetation differs from conventional and recomended by Cypress Semiconductors development flow for PSoC 6 devices. These applications are not recomended as a starting point for development and should not be considered as supported examples for PSoC 6 devices.
Examples provided to use with **ModusToolbox® Software Environment** are a recommended reference point to start development of MCUboot based bootloaders for PSoC 6 devices.
Refer to **Cypress Semiconductors** [github](https://github.com/cypresssemiconductorco) page to find examples.
1. MCUboot-Based Basic Bootloader [mtb-example-psoc6-mcuboot-basic](https://github.com/cypresssemiconductorco/mtb-example-psoc6-mcuboot-basic)
2. MCUboot-Based Bootloader with Rollback to Factory App in External Flash [mtb-example-anycloud-mcuboot-rollback](https://github.com/cypresssemiconductorco/mtb-example-anycloud-mcuboot-rollback)
### Solution description
There are two applications implemented:
* MCUBootApp - PSoC6 MCUboot-based bootloading application;
* BlinkyApp - simple PSoC6 blinking LED application which is a target of BOOT/UPGRADE;
The default flash map for MCUBootApp implemented is next:
* [0x10000000, 0x10018000] - MCUBootApp (bootloader) area;
* [0x10018000, 0x10028000] - primary slot for BlinkyApp;
* [0x10028000, 0x10038000] - secondary slot for BlinkyApp;
* [0x10038000, 0x10039000] - scratch area;
The flash map is defined through sysflash.h and cy_flash_map.c.
It is also possible to place secondary (upgrade) slots in external memory module. In this case primary slot can be doubled in size.
For more details about External Memory usage, please refer to separate guiding document `MCUBootApp/ExternalMemory.md`.
MCUBootApp checks image integrity with SHA256, image authenticity with EC256 digital signature verification and uses either completely software implementation of cryptographic functions or accelerated by hardware - both based on Mbed TLS Library.
### Downloading solution's assets
There is a set assets required:
* MCUBooot Library (root repository)
* PSoC6 Peripheral Drivers Library (PDL)
* Mbed TLS Cryptographic Library
Those are represented as submodules.
To retrieve source code with subsequent submodules pull:
git clone --recursive https://github.com/mcu-tools/mcuboot.git
Submodules can also be updated and initialized separately:
cd mcuboot
git submodule update --init --recursive
### Building solution
Root directory for build is **boot/cypress.**
This folder contains make files infrastructure for building both MCUboot Bootloader and sample BlinkyApp application used for Bootloader demo functionality.
Instructions on how to build and upload MCUBootApp bootloader application and sample user applocation are located in `Readme.md` files in corresponding folders.
Supported platforms for `MCUboot`, `BlinkyApp`:
* PSOC_062_2M
* PSOC_062_1M
* PSOC_062_512K
### Build environment troubleshooting
Following CLI / IDE are supported for project build:
* Cygwin on Windows systems
* unix style shells on *nix systems
* Eclipse / ModusToolbox ("makefile project from existing source")
*Make* - make sure it is added to system's `PATH` variable and correct path is first in the list;
*Python/Python3* - make sure you have correct path referenced in `PATH`;
*Msys2* - to use systems PATH navigate to msys2 folder, open `msys2_shell.cmd`, uncomment set `MSYS2_PATH_TYPE=inherit`, restart MSYS2 shell.
This will inherit system's PATH so should find `python3.7` installed in regular way as well as imgtool and its dependencies.

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################################################################################
# \file common_libs.mk
# \version 1.0
#
# \brief
# Makefile to describe libraries needed for Cypress MCUBoot based applications.
#
################################################################################
# \copyright
# Copyright 2018-2021 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
################################################################################
include host.mk
################################################################################
# PDL library
################################################################################
PSOC6_LIBS_PATH = $(PRJ_DIR)/libs
ifeq ($(CORE),CM0P)
CORE_SIFFX=m0plus
else
CORE_SIFFX=m4
endif
# Collect source files for PDL
SOURCES_PDL := $(wildcard $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/drivers/source/*.c)
SOURCES_PDL += $(wildcard $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/*.c)
# PDL startup related files
SOURCES_PDL_STARTUP := $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_$(CORE)/system_psoc6_c$(CORE_SIFFX).c
# PDL related include directories
INCLUDE_DIRS_PDL := $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/drivers/include
INCLUDE_DIRS_PDL += $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip
INCLUDE_DIRS_PDL += $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include
INCLUDE_DIRS_PDL += $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/cmsis/include
# PDL startup related files
INCLUDE_DIRS_PDL_STARTUP := $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB
# core-libs related include directories
INCLUDE_DIRS_CORE_LIB := $(PSOC6_LIBS_PATH)/core-lib/include
STARTUP_FILE := $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_$(CORE)/TOOLCHAIN_$(COMPILER)/startup_psoc6_$(PLATFORM_SUFFIX)_c$(CORE_SIFFX)
ifeq ($(COMPILER), GCC_ARM)
ASM_FILES_STARTUP := $(STARTUP_FILE).S
else
$(error Only GCC ARM is supported at this moment)
endif
# Collected source files for libraries
SOURCES_LIBS := $(SOURCES_PDL)
SOURCES_LIBS += $(SOURCES_PDL_STARTUP)
# Collected include directories for libraries
INCLUDE_DIRS_LIBS := $(addprefix -I,$(INCLUDE_DIRS_PDL))
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_PDL_STARTUP))
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_CORE_LIB))
ASM_FILES_PDL :=
ifeq ($(COMPILER), GCC_ARM)
ASM_FILES_PDL += $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S
else
$(error Only GCC ARM is supported at this moment)
endif
ASM_FILES_LIBS := $(ASM_FILES_PDL)
# Add define for PDL version
DEFINES_PDL += -DPDL_VERSION=$(PDL_VERSION)
DEFINES_LIBS := $(DEFINES_PLATFORM)
DEFINES_LIBS += $(DEFINES_PDL)

547
bootloader/mcuboot/boot/cypress/cy_flash_pal/cy_flash_map.c Normal file
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/*
* Copyright (c) 2018 Nordic Semiconductor ASA
* Copyright (c) 2020 Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
/*******************************************************************************/
#ifdef MCUBOOT_HAVE_ASSERT_H
#include "mcuboot_config/mcuboot_assert.h"
#else
#include <assert.h>
#endif
#include <stdbool.h>
#include <stdio.h>
#include <stdint.h>
#include "mcuboot_config/mcuboot_config.h"
#include "flash_map_backend/flash_map_backend.h"
#include <sysflash/sysflash.h>
#include "bootutil/bootutil_log.h"
#include "cy_pdl.h"
#ifdef CY_BOOT_USE_EXTERNAL_FLASH
#include "cy_smif_psoc6.h"
#endif
/*
* For now, we only support one flash device.
*
* Pick a random device ID for it that's unlikely to collide with
* anything "real".
*/
#define FLASH_DEVICE_ID 111
#define FLASH_MAP_ENTRY_MAGIC 0xd00dbeef
#define FLASH_AREA_IMAGE_SECTOR_SIZE FLASH_AREA_IMAGE_SCRATCH_SIZE
#ifndef CY_BOOTLOADER_START_ADDRESS
#define CY_BOOTLOADER_START_ADDRESS (0x10000000)
#endif
#ifndef CY_BOOT_INTERNAL_FLASH_ERASE_VALUE
/* This is the value of internal flash bytes after an erase */
#define CY_BOOT_INTERNAL_FLASH_ERASE_VALUE (0x00)
#endif
#ifndef CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE
/* This is the value of external flash bytes after an erase */
#define CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE (0xff)
#endif
#ifdef CY_FLASH_MAP_EXT_DESC
/* Nothing to be there when external FlashMap Descriptors are used */
#else
static struct flash_area bootloader =
{
.fa_id = FLASH_AREA_BOOTLOADER,
.fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
.fa_off = CY_BOOTLOADER_START_ADDRESS,
.fa_size = CY_BOOT_BOOTLOADER_SIZE
};
static struct flash_area primary_1 =
{
.fa_id = FLASH_AREA_IMAGE_PRIMARY(0),
.fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
.fa_off = CY_FLASH_BASE + CY_BOOT_BOOTLOADER_SIZE,
.fa_size = CY_BOOT_PRIMARY_1_SIZE
};
#ifndef CY_BOOT_USE_EXTERNAL_FLASH
static struct flash_area secondary_1 =
{
.fa_id = FLASH_AREA_IMAGE_SECONDARY(0),
.fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
.fa_off = CY_FLASH_BASE +\
CY_BOOT_BOOTLOADER_SIZE +\
CY_BOOT_PRIMARY_1_SIZE,
.fa_size = CY_BOOT_SECONDARY_1_SIZE
};
#else
static struct flash_area secondary_1 =
{
.fa_id = FLASH_AREA_IMAGE_SECONDARY(0),
.fa_device_id = FLASH_DEVICE_EXTERNAL_FLASH(CY_BOOT_EXTERNAL_DEVICE_INDEX),
.fa_off = CY_SMIF_BASE_MEM_OFFSET,
.fa_size = CY_BOOT_SECONDARY_1_SIZE
};
#endif
#if (MCUBOOT_IMAGE_NUMBER == 2) /* if dual-image */
static struct flash_area primary_2 =
{
.fa_id = FLASH_AREA_IMAGE_PRIMARY(1),
.fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
.fa_off = CY_FLASH_BASE +\
CY_BOOT_BOOTLOADER_SIZE +\
CY_BOOT_PRIMARY_1_SIZE +\
CY_BOOT_SECONDARY_1_SIZE,
.fa_size = CY_BOOT_PRIMARY_2_SIZE
};
static struct flash_area secondary_2 =
{
.fa_id = FLASH_AREA_IMAGE_SECONDARY(1),
/* it is for external flash memory
.fa_device_id = FLASH_DEVICE_EXTERNAL_FLASH(CY_BOOT_EXTERNAL_DEVICE_INDEX), */
#ifndef CY_BOOT_USE_EXTERNAL_FLASH
.fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
.fa_off = CY_FLASH_BASE +\
CY_BOOT_BOOTLOADER_SIZE +\
CY_BOOT_PRIMARY_1_SIZE +\
CY_BOOT_SECONDARY_1_SIZE +\
CY_BOOT_PRIMARY_2_SIZE,
#else
.fa_device_id = FLASH_DEVICE_EXTERNAL_FLASH(CY_BOOT_EXTERNAL_DEVICE_INDEX),
.fa_off = CY_SMIF_BASE_MEM_OFFSET + 0x40000,
#endif
.fa_size = CY_BOOT_SECONDARY_2_SIZE
};
#endif
#endif
#ifdef MCUBOOT_SWAP_USING_SCRATCH
static struct flash_area scratch =
{
.fa_id = FLASH_AREA_IMAGE_SCRATCH,
.fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
#if (MCUBOOT_IMAGE_NUMBER == 1) /* if single-image */
.fa_off = CY_FLASH_BASE +\
CY_BOOT_BOOTLOADER_SIZE +\
CY_BOOT_PRIMARY_1_SIZE +\
CY_BOOT_SECONDARY_1_SIZE,
#elif (MCUBOOT_IMAGE_NUMBER == 2) /* if dual-image */
.fa_off = CY_FLASH_BASE +\
CY_BOOT_BOOTLOADER_SIZE +\
CY_BOOT_PRIMARY_1_SIZE +\
CY_BOOT_SECONDARY_1_SIZE +\
CY_BOOT_PRIMARY_2_SIZE +\
CY_BOOT_SECONDARY_2_SIZE,
#endif
.fa_size = CY_BOOT_SCRATCH_SIZE
};
#endif
#ifdef CY_FLASH_MAP_EXT_DESC
/* Use external Flash Map Descriptors */
extern struct flash_area *boot_area_descs[];
#else
struct flash_area *boot_area_descs[] =
{
&bootloader,
&primary_1,
&secondary_1,
#if (MCUBOOT_IMAGE_NUMBER == 2) /* if dual-image */
&primary_2,
&secondary_2,
#endif
#ifdef MCUBOOT_SWAP_USING_SCRATCH
&scratch,
#endif
NULL
};
#endif
/* Returns device flash start based on supported fa_id */
int flash_device_base(uint8_t fd_id, uintptr_t *ret)
{
if (fd_id != FLASH_DEVICE_INTERNAL_FLASH) {
BOOT_LOG_ERR("invalid flash ID %d; expected %d",
fd_id, FLASH_DEVICE_INTERNAL_FLASH);
return -1;
}
*ret = CY_FLASH_BASE;
return 0;
}
/* Opens the area for use. id is one of the `fa_id`s */
int flash_area_open(uint8_t id, const struct flash_area **fa)
{
int ret = -1;
uint32_t i = 0;
while(NULL != boot_area_descs[i])
{
if(id == boot_area_descs[i]->fa_id)
{
*fa = boot_area_descs[i];
ret = 0;
break;
}
i++;
}
return ret;
}
void flash_area_close(const struct flash_area *fa)
{
(void)fa;/* Nothing to do there */
}
/*
* Reads `len` bytes of flash memory at `off` to the buffer at `dst`
*/
int flash_area_read(const struct flash_area *fa, uint32_t off, void *dst,
uint32_t len)
{
int rc = 0;
size_t addr;
/* check if requested offset not less then flash area (fa) start */
assert(off < fa->fa_off);
assert(off + len < fa->fa_off);
/* convert to absolute address inside a device*/
addr = fa->fa_off + off;
if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
{
/* flash read by simple memory copying */
memcpy((void *)dst, (const void*)addr, (size_t)len);
}
#ifdef CY_BOOT_USE_EXTERNAL_FLASH
else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
{
rc = psoc6_smif_read(fa, addr, dst, len);
}
#endif
else
{
/* incorrect/non-existing flash device id */
rc = -1;
}
if (rc != 0) {
BOOT_LOG_ERR("Flash area read error, rc = %d", (int)rc);
}
return rc;
}
/*
* Writes `len` bytes of flash memory at `off` from the buffer at `src`
*/
int flash_area_write(const struct flash_area *fa, uint32_t off,
const void *src, uint32_t len)
{
cy_en_flashdrv_status_t rc = CY_FLASH_DRV_SUCCESS;
size_t write_start_addr;
size_t write_end_addr;
const uint32_t * row_ptr = NULL;
assert(off < fa->fa_off);
assert(off + len < fa->fa_off);
/* convert to absolute address inside a device */
write_start_addr = fa->fa_off + off;
write_end_addr = fa->fa_off + off + len;
if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
{
uint32_t row_number = 0;
uint32_t row_addr = 0;
assert(!(len % CY_FLASH_SIZEOF_ROW));
assert(!(write_start_addr % CY_FLASH_SIZEOF_ROW));
row_number = (write_end_addr - write_start_addr) / CY_FLASH_SIZEOF_ROW;
row_addr = write_start_addr;
row_ptr = (uint32_t *) src;
for (uint32_t i = 0; i < row_number; i++)
{
rc = Cy_Flash_WriteRow(row_addr, row_ptr);
row_addr += (uint32_t) CY_FLASH_SIZEOF_ROW;
row_ptr = row_ptr + CY_FLASH_SIZEOF_ROW / 4;
}
}
#ifdef CY_BOOT_USE_EXTERNAL_FLASH
else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
{
rc = psoc6_smif_write(fa, write_start_addr, src, len);
}
#endif
else
{
/* incorrect/non-existing flash device id */
rc = -1;
}
return (int) rc;
}
/*< Erases `len` bytes of flash memory at `off` */
int flash_area_erase(const struct flash_area *fa, uint32_t off, uint32_t len)
{
cy_en_flashdrv_status_t rc = CY_FLASH_DRV_SUCCESS;
size_t erase_start_addr;
size_t erase_end_addr;
assert(off < fa->fa_off);
assert(off + len < fa->fa_off);
assert(!(len % CY_FLASH_SIZEOF_ROW));
/* convert to absolute address inside a device*/
erase_start_addr = fa->fa_off + off;
erase_end_addr = fa->fa_off + off + len;
if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
{
int row_number = 0;
uint32_t row_addr = 0;
row_number = (erase_end_addr - erase_start_addr) / CY_FLASH_SIZEOF_ROW;
while (row_number != 0)
{
row_number--;
row_addr = erase_start_addr + row_number * (uint32_t) CY_FLASH_SIZEOF_ROW;
rc = Cy_Flash_EraseRow(row_addr);
}
}
#ifdef CY_BOOT_USE_EXTERNAL_FLASH
else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
{
rc = psoc6_smif_erase(erase_start_addr, len);
}
#endif
else
{
/* incorrect/non-existing flash device id */
rc = -1;
}
return (int) rc;
}
/*< Returns this `flash_area`s alignment */
uint32_t flash_area_align(const struct flash_area *fa)
{
int ret = -1;
if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
{
ret = CY_FLASH_ALIGN;
}
#ifdef CY_BOOT_USE_EXTERNAL_FLASH
else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
{
return qspi_get_prog_size();
}
#endif
else
{
/* incorrect/non-existing flash device id */
ret = -1;
}
return ret;
}
#ifdef MCUBOOT_USE_FLASH_AREA_GET_SECTORS
/*< Initializes an array of flash_area elements for the slot's sectors */
int flash_area_to_sectors(int idx, int *cnt, struct flash_area *fa)
{
int rc = 0;
if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
{
(void)idx;
(void)cnt;
rc = 0;
}
#ifdef CY_BOOT_USE_EXTERNAL_FLASH
else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
{
(void)idx;
(void)cnt;
rc = 0;
}
#endif
else
{
/* incorrect/non-existing flash device id */
rc = -1;
}
return rc;
}
#endif
/*
* This depends on the mappings defined in sysflash.h.
* MCUBoot uses continuous numbering for the primary slot, the secondary slot,
* and the scratch while zephyr might number it differently.
*/
int flash_area_id_from_multi_image_slot(int image_index, int slot)
{
switch (slot) {
case 0: return FLASH_AREA_IMAGE_PRIMARY(image_index);
case 1: return FLASH_AREA_IMAGE_SECONDARY(image_index);
case 2: return FLASH_AREA_IMAGE_SCRATCH;
}
return -1; /* flash_area_open will fail on that */
}
int flash_area_id_from_image_slot(int slot)
{
return flash_area_id_from_multi_image_slot(0, slot);
}
int flash_area_id_to_multi_image_slot(int image_index, int area_id)
{
if (area_id == FLASH_AREA_IMAGE_PRIMARY(image_index)) {
return 0;
}
if (area_id == FLASH_AREA_IMAGE_SECONDARY(image_index)) {
return 1;
}
return -1;
}
uint8_t flash_area_erased_val(const struct flash_area *fap)
{
int ret = 0;
if (fap->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
{
ret = CY_BOOT_INTERNAL_FLASH_ERASE_VALUE;
}
#ifdef CY_BOOT_USE_EXTERNAL_FLASH
else if ((fap->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
{
ret = CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE;
}
#endif
else
{
assert(false) ;
}
return ret ;
}
int flash_area_read_is_empty(const struct flash_area *fa, uint32_t off,
void *dst, uint32_t len)
{
uint8_t *mem_dest;
int rc;
mem_dest = (uint8_t *)dst;
rc = flash_area_read(fa, off, dst, len);
if (rc) {
return -1;
}
for (uint8_t i = 0; i < len; i++) {
if (mem_dest[i] != flash_area_erased_val(fa)) {
return 0;
}
}
return 1;
}
#ifdef MCUBOOT_USE_FLASH_AREA_GET_SECTORS
int flash_area_get_sectors(int idx, uint32_t *cnt, struct flash_sector *ret)
{
int rc = 0;
uint32_t i = 0;
struct flash_area *fa = NULL;
while(NULL != boot_area_descs[i])
{
if(idx == boot_area_descs[i]->fa_id)
{
fa = boot_area_descs[i];
break;
}
i++;
}
if(NULL != boot_area_descs[i])
{
size_t sector_size = 0;
if(fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
{
sector_size = CY_FLASH_SIZEOF_ROW;
}
#ifdef CY_BOOT_USE_EXTERNAL_FLASH
else if((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
{
/* implement for SMIF */
/* lets assume they are equal */
sector_size = CY_FLASH_SIZEOF_ROW;
}
#endif
else
{
rc = -1;
}
if(0 == rc)
{
uint32_t addr = 0;
size_t sectors_n = 0;
sectors_n = (fa->fa_size + (sector_size - 1)) / sector_size;
assert(sectors_n <= *cnt);
addr = fa->fa_off;
for(i = 0; i < sectors_n; i++)
{
ret[i].fs_size = sector_size ;
ret[i].fs_off = addr ;
addr += sector_size ;
}
*cnt = sectors_n;
}
}
else
{
rc = -1;
}
return rc;
}
#endif

143
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/***************************************************************************//**
* \file cy_smif_psoc6.c
* \version 1.0
*
* \brief
* This is the source file of external flash driver adoption layer between PSoC6
* and standard MCUBoot code.
*
********************************************************************************
* \copyright
*
* (c) 2020, Cypress Semiconductor Corporation
* or a subsidiary of Cypress Semiconductor Corporation. All rights
* reserved.
*
* This software, including source code, documentation and related
* materials ("Software"), is owned by Cypress Semiconductor
* Corporation or one of its subsidiaries ("Cypress") and is protected by
* and subject to worldwide patent protection (United States and foreign),
* United States copyright laws and international treaty provisions.
* Therefore, you may use this Software only as provided in the license
* agreement accompanying the software package from which you
* obtained this Software ("EULA").
*
* If no EULA applies, Cypress hereby grants you a personal, non-
* exclusive, non-transferable license to copy, modify, and compile the
* Software source code solely for use in connection with Cypress?s
* integrated circuit products. Any reproduction, modification, translation,
* compilation, or representation of this Software except as specified
* above is prohibited without the express written permission of Cypress.
*
* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO
* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING,
* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE. Cypress reserves the right to make
* changes to the Software without notice. Cypress does not assume any
* liability arising out of the application or use of the Software or any
* product or circuit described in the Software. Cypress does not
* authorize its products for use in any products where a malfunction or
* failure of the Cypress product may reasonably be expected to result in
* significant property damage, injury or death ("High Risk Product"). By
* including Cypress's product in a High Risk Product, the manufacturer
* of such system or application assumes all risk of such use and in doing
* so agrees to indemnify Cypress against all liability.
*
******************************************************************************/
#include "string.h"
#include "stdlib.h"
#include "stdbool.h"
#ifdef MCUBOOT_HAVE_ASSERT_H
#include "mcuboot_config/mcuboot_assert.h"
#else
#include <assert.h>
#endif
#include "flash_map_backend/flash_map_backend.h"
#include <sysflash/sysflash.h>
#include "cy_device_headers.h"
#include "cy_smif_psoc6.h"
#include "cy_flash.h"
#include "cy_syspm.h"
#include "flash_qspi.h"
#define PSOC6_WR_SUCCESS (0)
#define PSOC6_WR_ERROR_INVALID_PARAMETER (1)
#define PSOC6_WR_ERROR_FLASH_WRITE (2)
#define PSOC6_FLASH_ERASE_BLOCK_SIZE CY_FLASH_SIZEOF_ROW /* PSoC6 Flash erases by Row */
int psoc6_smif_read(const struct flash_area *fap,
off_t addr,
void *data,
size_t len)
{
int rc = -1;
cy_stc_smif_mem_config_t *cfg;
cy_en_smif_status_t st;
uint32_t address;
cfg = qspi_get_memory_config(FLASH_DEVICE_GET_EXT_INDEX(fap->fa_device_id));
address = addr - CY_SMIF_BASE_MEM_OFFSET;
st = Cy_SMIF_MemRead(qspi_get_device(), cfg, address, data, len, qspi_get_context());
if (st == CY_SMIF_SUCCESS) {
rc = 0;
}
return rc;
}
int psoc6_smif_write(const struct flash_area *fap,
off_t addr,
const void *data,
size_t len)
{
int rc = -1;
cy_en_smif_status_t st;
cy_stc_smif_mem_config_t *cfg;
uint32_t address;
cfg = qspi_get_memory_config(FLASH_DEVICE_GET_EXT_INDEX(fap->fa_device_id));
address = addr - CY_SMIF_BASE_MEM_OFFSET;
st = Cy_SMIF_MemWrite(qspi_get_device(), cfg, address, data, len, qspi_get_context());
if (st == CY_SMIF_SUCCESS) {
rc = 0;
}
return rc;
}
int psoc6_smif_erase(off_t addr, size_t size)
{
int rc = -1;
cy_en_smif_status_t st;
uint32_t address;
/* It is erase sector-only
*
* There is no power-safe way to erase flash partially
* this leads upgrade slots have to be at least
* eraseSectorSize far from each other;
*/
cy_stc_smif_mem_config_t *memCfg = qspi_get_memory_config(0);
address = (addr - CY_SMIF_BASE_MEM_OFFSET ) & ~((uint32_t)(memCfg->deviceCfg->eraseSize - 1u));
(void)size;
st = Cy_SMIF_MemEraseSector(qspi_get_device(),
memCfg,
address,
memCfg->deviceCfg->eraseSize,
qspi_get_context());
if (st == CY_SMIF_SUCCESS) {
rc = 0;
}
return rc;
}

494
bootloader/mcuboot/boot/cypress/cy_flash_pal/flash_qspi/flash_qspi.c Normal file
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/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
/***************************************************************************//**
* \file flash_qspi.c
* \version 1.0
*
* \brief
* This is the source file of external flash driver adaptation layer between PSoC6
* and standard MCUBoot code.
*
********************************************************************************
* \copyright
*
* (c) 2020, Cypress Semiconductor Corporation
* or a subsidiary of Cypress Semiconductor Corporation. All rights
* reserved.
*
* This software, including source code, documentation and related
* materials ("Software"), is owned by Cypress Semiconductor
* Corporation or one of its subsidiaries ("Cypress") and is protected by
* and subject to worldwide patent protection (United States and foreign),
* United States copyright laws and international treaty provisions.
* Therefore, you may use this Software only as provided in the license
* agreement accompanying the software package from which you
* obtained this Software ("EULA").
*
* If no EULA applies, Cypress hereby grants you a personal, non-
* exclusive, non-transferable license to copy, modify, and compile the
* Software source code solely for use in connection with Cypress?s
* integrated circuit products. Any reproduction, modification, translation,
* compilation, or representation of this Software except as specified
* above is prohibited without the express written permission of Cypress.
*
* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO
* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING,
* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE. Cypress reserves the right to make
* changes to the Software without notice. Cypress does not assume any
* liability arising out of the application or use of the Software or any
* product or circuit described in the Software. Cypress does not
* authorize its products for use in any products where a malfunction or
* failure of the Cypress product may reasonably be expected to result in
* significant property damage, injury or death ("High Risk Product"). By
* including Cypress's product in a High Risk Product, the manufacturer
* of such system or application assumes all risk of such use and in doing
* so agrees to indemnify Cypress against all liability.
*
******************************************************************************/
#include "cy_pdl.h"
#include <stdio.h>
#include "flash_qspi.h"
#define CY_SMIF_SYSCLK_HFCLK_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_4
/* This is the board specific stuff that should align with your board.
*
* QSPI resources:
*
* SS0 - P11_2
* SS1 - P11_1
* SS2 - P11_0
* SS3 - P12_4
*
* D3 - P11_3
* D2 - P11_4
* D1 - P11_5
* D0 - P11_6
*
* SCK - P11_7
*
* SMIF Block - SMIF0
*
*/
/* SMIF SlaveSelect Configurations */
struct qspi_ss_config
{
GPIO_PRT_Type* SS_Port;
int SS_Pin;
en_hsiom_sel_t SS_Mux;
};
#if (defined(PSOC_064_2M) || \
defined(PSOC_064_1M) || \
defined(PSOC_062_2M) || \
defined(PSOC_062_1M))
#define CY_BOOTLOADER_SMIF_SS_CFG_NUM 4
#elif defined(PSOC_064_512K) || defined(PSOC_062_512K)
#define CY_BOOTLOADER_SMIF_SS_CFG_NUM 3
#else
#error "Platform device name is unsupported."
#endif
struct qspi_ss_config qspi_SS_Configuration[CY_BOOTLOADER_SMIF_SS_CFG_NUM] =
{
{
.SS_Port = GPIO_PRT11,
.SS_Pin = 2,
.SS_Mux = P11_2_SMIF_SPI_SELECT0
},
{
.SS_Port = GPIO_PRT11,
.SS_Pin = 1,
.SS_Mux = P11_1_SMIF_SPI_SELECT1
},
{
.SS_Port = GPIO_PRT11,
.SS_Pin = 0,
.SS_Mux = P11_0_SMIF_SPI_SELECT2
},
#if(CY_BOOTLOADER_SMIF_SS_CFG_NUM > 3)
{
.SS_Port = GPIO_PRT12,
.SS_Pin = 4,
.SS_Mux = P12_4_SMIF_SPI_SELECT3
}
#endif
};
static GPIO_PRT_Type *D3Port = GPIO_PRT11;
static int D3Pin = 3;
static en_hsiom_sel_t D3MuxPort = P11_3_SMIF_SPI_DATA3;
static GPIO_PRT_Type *D2Port = GPIO_PRT11;
static int D2Pin = 4;
static en_hsiom_sel_t D2MuxPort = P11_4_SMIF_SPI_DATA2;
static GPIO_PRT_Type *D1Port = GPIO_PRT11;
static int D1Pin = 5;
static en_hsiom_sel_t D1MuxPort = P11_5_SMIF_SPI_DATA1;
static GPIO_PRT_Type *D0Port = GPIO_PRT11;
static int D0Pin = 6;
static en_hsiom_sel_t D0MuxPort = P11_6_SMIF_SPI_DATA0;
static GPIO_PRT_Type *SCKPort = GPIO_PRT11;
static int SCKPin = 7;
static en_hsiom_sel_t SCKMuxPort = P11_7_SMIF_SPI_CLK;
static SMIF_Type *QSPIPort = SMIF0;
cy_stc_smif_mem_cmd_t sfdpcmd =
{
.command = 0x5A,
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
.addrWidth = CY_SMIF_WIDTH_SINGLE,
.mode = 0xFFFFFFFFU,
.dummyCycles = 8,
.dataWidth = CY_SMIF_WIDTH_SINGLE,
};
static cy_stc_smif_mem_cmd_t rdcmd0;
static cy_stc_smif_mem_cmd_t wrencmd0;
static cy_stc_smif_mem_cmd_t wrdiscmd0;
static cy_stc_smif_mem_cmd_t erasecmd0;
static cy_stc_smif_mem_cmd_t chiperasecmd0;
static cy_stc_smif_mem_cmd_t pgmcmd0;
static cy_stc_smif_mem_cmd_t readsts0;
static cy_stc_smif_mem_cmd_t readstsqecmd0;
static cy_stc_smif_mem_cmd_t writestseqcmd0;
static cy_stc_smif_mem_device_cfg_t dev_sfdp_0 =
{
.numOfAddrBytes = 4,
.readSfdpCmd = &sfdpcmd,
.readCmd = &rdcmd0,
.writeEnCmd = &wrencmd0,
.writeDisCmd = &wrdiscmd0,
.programCmd = &pgmcmd0,
.eraseCmd = &erasecmd0,
.chipEraseCmd = &chiperasecmd0,
.readStsRegWipCmd = &readsts0,
.readStsRegQeCmd = &readstsqecmd0,
.writeStsRegQeCmd = &writestseqcmd0,
};
static cy_stc_smif_mem_config_t mem_sfdp_0 =
{
/* The base address the memory slave is mapped to in the PSoC memory map.
Valid when the memory-mapped mode is enabled. */
.baseAddress = 0x18000000U,
/* The size allocated in the PSoC memory map, for the memory slave device.
The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
/* .memMappedSize = 0x4000000U, */
.flags = CY_SMIF_FLAG_DETECT_SFDP,
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
.dataSelect = CY_SMIF_DATA_SEL0,
.deviceCfg = &dev_sfdp_0
};
cy_stc_smif_mem_config_t *mems_sfdp[1] =
{
&mem_sfdp_0
};
/* make it exported if used in TOC (cy_serial_flash_prog.c) */
/* cy_stc_smif_block_config_t smifBlockConfig_sfdp = */
static cy_stc_smif_block_config_t smifBlockConfig_sfdp =
{
.memCount = 1,
.memConfig = mems_sfdp,
};
static cy_stc_smif_block_config_t *smif_blk_config;
static cy_stc_smif_context_t QSPI_context;
cy_stc_smif_config_t const QSPI_config =
{
.mode = CY_SMIF_NORMAL,
.deselectDelay = 1,
.rxClockSel = CY_SMIF_SEL_INV_INTERNAL_CLK,
.blockEvent = CY_SMIF_BUS_ERROR
};
cy_stc_sysint_t smifIntConfig =
{/* ATTENTION: make sure proper Interrupts configured for CM0p or M4 cores */
.intrSrc = NvicMux7_IRQn,
.cm0pSrc = smif_interrupt_IRQn,
.intrPriority = 1
};
/* SMIF pinouts configurations */
static cy_stc_gpio_pin_config_t QSPI_SS_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = P11_2_SMIF_SPI_SELECT0, /* lets use SS0 by default */
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t QSPI_DATA3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = P11_3_SMIF_SPI_DATA3,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t QSPI_DATA2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = P11_4_SMIF_SPI_DATA2,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t QSPI_DATA1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = P11_5_SMIF_SPI_DATA1,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t QSPI_DATA0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = P11_6_SMIF_SPI_DATA0,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t QSPI_SCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = P11_7_SMIF_SPI_CLK,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
void Isr_SMIF(void)
{
Cy_SMIF_Interrupt(QSPIPort, &QSPI_context);
}
cy_en_smif_status_t qspi_init_hardware()
{
cy_en_smif_status_t st;
Cy_GPIO_Pin_Init(D3Port, D3Pin, &QSPI_DATA3_config);
Cy_GPIO_SetHSIOM(D3Port, D3Pin, D3MuxPort);
Cy_GPIO_Pin_Init(D2Port, D2Pin, &QSPI_DATA2_config);
Cy_GPIO_SetHSIOM(D2Port, D2Pin, D2MuxPort);
Cy_GPIO_Pin_Init(D1Port, D1Pin, &QSPI_DATA1_config);
Cy_GPIO_SetHSIOM(D1Port, D1Pin, D1MuxPort);
Cy_GPIO_Pin_Init(D0Port, D0Pin, &QSPI_DATA0_config);
Cy_GPIO_SetHSIOM(D0Port, D0Pin, D0MuxPort);
Cy_GPIO_Pin_Init(SCKPort, SCKPin, &QSPI_SCK_config);
Cy_GPIO_SetHSIOM(SCKPort, SCKPin, SCKMuxPort);
Cy_SysClk_ClkHfSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH2, CY_SYSCLK_CLKHF_IN_CLKPATH0);
Cy_SysClk_ClkHfSetDivider(CY_SYSCLK_CLKHF_IN_CLKPATH2, CY_SMIF_SYSCLK_HFCLK_DIVIDER);
Cy_SysClk_ClkHfEnable(CY_SYSCLK_CLKHF_IN_CLKPATH2);
/*
* Setup the interrupt for the SMIF block. For the CM0 there
* is a two stage process to setup the interrupts.
*/
Cy_SysInt_Init(&smifIntConfig, Isr_SMIF);
st = Cy_SMIF_Init(QSPIPort, &QSPI_config, 1000, &QSPI_context);
if (st != CY_SMIF_SUCCESS)
{
return st;
}
NVIC_EnableIRQ(smifIntConfig.intrSrc); /* Finally, Enable the SMIF interrupt */
Cy_SMIF_Enable(QSPIPort, &QSPI_context);
return CY_SMIF_SUCCESS;
}
cy_stc_smif_mem_config_t *qspi_get_memory_config(int index)
{
return smif_blk_config->memConfig[index];
}
SMIF_Type *qspi_get_device()
{
return QSPIPort;
}
cy_stc_smif_context_t *qspi_get_context()
{
return &QSPI_context;
}
cy_en_smif_status_t qspi_init(cy_stc_smif_block_config_t *blk_config)
{
cy_en_smif_status_t st;
st = qspi_init_hardware();
if (st == CY_SMIF_SUCCESS)
{
smif_blk_config = blk_config;
st = Cy_SMIF_MemInit(QSPIPort, smif_blk_config, &QSPI_context);
}
return st;
}
cy_en_smif_status_t qspi_init_sfdp(uint32_t smif_id)
{
cy_en_smif_status_t stat = CY_SMIF_SUCCESS;
cy_stc_smif_mem_config_t **memCfg = smifBlockConfig_sfdp.memConfig;
GPIO_PRT_Type *SS_Port;
int SS_Pin;
en_hsiom_sel_t SS_MuxPort;
switch(smif_id)
{
case 1:
(*memCfg)->slaveSelect = CY_SMIF_SLAVE_SELECT_0;
break;
case 2:
(*memCfg)->slaveSelect = CY_SMIF_SLAVE_SELECT_1;
break;
case 3:
(*memCfg)->slaveSelect = CY_SMIF_SLAVE_SELECT_2;
break;
#if(CY_BOOTLOADER_SMIF_SS_CFG_NUM > 3)
case 4:
(*memCfg)->slaveSelect = CY_SMIF_SLAVE_SELECT_3;
break;
#endif
default:
stat = -1;
break;
}
if(CY_SMIF_SUCCESS == stat)
{
SS_Port = qspi_SS_Configuration[smif_id-1].SS_Port;
SS_Pin = qspi_SS_Configuration[smif_id-1].SS_Pin;
SS_MuxPort = qspi_SS_Configuration[smif_id-1].SS_Mux;
QSPI_SS_config.hsiom = SS_MuxPort;
Cy_GPIO_Pin_Init(SS_Port, SS_Pin, &QSPI_SS_config);
Cy_GPIO_SetHSIOM(SS_Port, SS_Pin, SS_MuxPort);
stat = qspi_init(&smifBlockConfig_sfdp);
}
return stat;
}
uint32_t qspi_get_prog_size(void)
{
cy_stc_smif_mem_config_t **memCfg = smifBlockConfig_sfdp.memConfig;
return (*memCfg)->deviceCfg->programSize;
}
uint32_t qspi_get_erase_size(void)
{
cy_stc_smif_mem_config_t **memCfg = smifBlockConfig_sfdp.memConfig;
return (*memCfg)->deviceCfg->eraseSize;
}
uint32_t qspi_get_mem_size(void)
{
cy_stc_smif_mem_config_t **memCfg = smifBlockConfig_sfdp.memConfig;
return (*memCfg)->deviceCfg->memSize;
}
void qspi_deinit(uint32_t smif_id)
{
Cy_SMIF_MemDeInit(QSPIPort);
Cy_SMIF_Disable(QSPIPort);
Cy_SysClk_ClkHfDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2);
NVIC_DisableIRQ(smifIntConfig.intrSrc);
Cy_SysInt_DisconnectInterruptSource(smifIntConfig.intrSrc, smifIntConfig.cm0pSrc);
Cy_GPIO_Port_Deinit(qspi_SS_Configuration[smif_id-1].SS_Port);
Cy_GPIO_Port_Deinit(SCKPort);
Cy_GPIO_Port_Deinit(D0Port);
Cy_GPIO_Port_Deinit(D1Port);
Cy_GPIO_Port_Deinit(D2Port);
Cy_GPIO_Port_Deinit(D3Port);
}

70
bootloader/mcuboot/boot/cypress/cy_flash_pal/flash_qspi/flash_qspi.h Normal file
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/***************************************************************************//**
* \file flash_qspi.h
* \version 1.0
*
* \brief
* This is the header file for PSoC6 external flash driver adoption layer.
*
********************************************************************************
* \copyright
*
* © 2020, Cypress Semiconductor Corporation
* or a subsidiary of Cypress Semiconductor Corporation. All rights
* reserved.
*
* This software, including source code, documentation and related
* materials ("Software"), is owned by Cypress Semiconductor
* Corporation or one of its subsidiaries ("Cypress") and is protected by
* and subject to worldwide patent protection (United States and foreign),
* United States copyright laws and international treaty provisions.
* Therefore, you may use this Software only as provided in the license
* agreement accompanying the software package from which you
* obtained this Software ("EULA").
*
* If no EULA applies, Cypress hereby grants you a personal, non-
* exclusive, non-transferable license to copy, modify, and compile the
* Software source code solely for use in connection with Cypress?s
* integrated circuit products. Any reproduction, modification, translation,
* compilation, or representation of this Software except as specified
* above is prohibited without the express written permission of Cypress.
*
* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO
* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING,
* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE. Cypress reserves the right to make
* changes to the Software without notice. Cypress does not assume any
* liability arising out of the application or use of the Software or any
* product or circuit described in the Software. Cypress does not
* authorize its products for use in any products where a malfunction or
* failure of the Cypress product may reasonably be expected to result in
* significant property damage, injury or death ("High Risk Product"). By
* including Cypress's product in a High Risk Product, the manufacturer
* of such system or application assumes all risk of such use and in doing
* so agrees to indemnify Cypress against all liability.
*
******************************************************************************/
#ifndef __FLASH_QSPI_H__
#define __FLASH_QSPI_H__
#include <stdint.h>
#include "cy_pdl.h"
/* make it exported if used in TOC (cy_serial_flash_prog.c) */
/* cy_stc_smif_block_config_t smifBlockConfig_sfdp; */
cy_en_smif_status_t qspi_init_sfdp(uint32_t smif_id);
cy_en_smif_status_t qspi_init(cy_stc_smif_block_config_t *blk_config);
cy_en_smif_status_t qspi_init_hardware(void);
uint32_t qspi_get_prog_size(void);
uint32_t qspi_get_erase_size(void);
uint32_t qspi_get_mem_size(void);
SMIF_Type *qspi_get_device(void);
cy_stc_smif_context_t *qspi_get_context(void);
cy_stc_smif_mem_config_t *qspi_get_memory_config(int index);
void qspi_dump_device(cy_stc_smif_mem_device_cfg_t *dev);
void qspi_deinit(uint32_t smif_id);
#endif /* __FLASH_QSPI_H__ */

64
bootloader/mcuboot/boot/cypress/cy_flash_pal/include/cy_smif_psoc6.h Normal file
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/***************************************************************************//**
* \file cy_smif_psoc6.h
* \version 1.0
*
* \brief
* This is the header file for PSoC6 SMIF driver adoption layer.
*
********************************************************************************
* \copyright
*
* © 2019, Cypress Semiconductor Corporation
* or a subsidiary of Cypress Semiconductor Corporation. All rights
* reserved.
*
* This software, including source code, documentation and related
* materials ("Software"), is owned by Cypress Semiconductor
* Corporation or one of its subsidiaries ("Cypress") and is protected by
* and subject to worldwide patent protection (United States and foreign),
* United States copyright laws and international treaty provisions.
* Therefore, you may use this Software only as provided in the license
* agreement accompanying the software package from which you
* obtained this Software ("EULA").
*
* If no EULA applies, Cypress hereby grants you a personal, non-
* exclusive, non-transferable license to copy, modify, and compile the
* Software source code solely for use in connection with Cypress?s
* integrated circuit products. Any reproduction, modification, translation,
* compilation, or representation of this Software except as specified
* above is prohibited without the express written permission of Cypress.
*
* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO
* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING,
* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE. Cypress reserves the right to make
* changes to the Software without notice. Cypress does not assume any
* liability arising out of the application or use of the Software or any
* product or circuit described in the Software. Cypress does not
* authorize its products for use in any products where a malfunction or
* failure of the Cypress product may reasonably be expected to result in
* significant property damage, injury or death ("High Risk Product"). By
* including Cypress's product in a High Risk Product, the manufacturer
* of such system or application assumes all risk of such use and in doing
* so agrees to indemnify Cypress against all liability.
*
******************************************************************************/
#ifndef CY_SMIF_PSOC6_H_
#define CY_SMIF_PSOC6_H_
#include "stddef.h"
#include "stdbool.h"
#include "flash_qspi.h"
#ifndef off_t
typedef long int off_t;
#endif
int psoc6_smif_read(const struct flash_area *fap, off_t addr, void *data, size_t len);
int psoc6_smif_write(const struct flash_area *fap, off_t addr, const void *data, size_t len);
int psoc6_smif_erase(off_t addr, size_t size);
#endif /* CY_SMIF_PSOC6_H_ */

195
bootloader/mcuboot/boot/cypress/cy_flash_pal/include/flash_map_backend/flash_map_backend.h Normal file
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/*
* Copyright (c) 2018 Nordic Semiconductor ASA
* Copyright (c) 2015 Runtime Inc
* Copyright (c) 2020 Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* KIND, either express or implied. See the License for the
* specific language governing permissions and limitations
* under the License.
*/
/*******************************************************************************/
#ifndef __FLASH_MAP_BACKEND_H__
#define __FLASH_MAP_BACKEND_H__
#include <mcuboot_config/mcuboot_config.h>
#include "cy_flash.h"
#define FLASH_DEVICE_INDEX_MASK (0x7F)
#define FLASH_DEVICE_GET_EXT_INDEX(n) ((n) & FLASH_DEVICE_INDEX_MASK)
#define FLASH_DEVICE_EXTERNAL_FLAG (0x80)
#define FLASH_DEVICE_INTERNAL_FLASH (0x7F)
#define FLASH_DEVICE_EXTERNAL_FLASH(index) (FLASH_DEVICE_EXTERNAL_FLAG | index)
#ifndef CY_BOOT_EXTERNAL_DEVICE_INDEX
/* assume first(one) SMIF device is used */
#define CY_BOOT_EXTERNAL_DEVICE_INDEX (0)
#endif
/**
*
* Provides abstraction of flash regions for type of use.
* I.e. dude where's my image?
*
* System will contain a map which contains flash areas. Every
* region will contain flash identifier, offset within flash and length.
*
* 1. This system map could be in a file within filesystem (Initializer
* must know/figure out where the filesystem is at).
* 2. Map could be at fixed location for project (compiled to code)
* 3. Map could be at specific place in flash (put in place at mfg time).
*
* Note that the map you use must be valid for BSP it's for,
* match the linker scripts when platform executes from flash,
* and match the target offset specified in download script.
*/
#include <inttypes.h>
/**
* @brief Structure describing an area on a flash device.
*
* Multiple flash devices may be available in the system, each of
* which may have its own areas. For this reason, flash areas track
* which flash device they are part of.
*/
struct flash_area {
/**
* This flash area's ID; unique in the system.
*/
uint8_t fa_id;
/**
* ID of the flash device this area is a part of.
*/
uint8_t fa_device_id;
uint16_t pad16;
/**
* This area's offset, relative to the beginning of its flash
* device's storage.
*/
uint32_t fa_off;
/**
* This area's size, in bytes.
*/
uint32_t fa_size;
};
static inline uint8_t flash_area_get_id(const struct flash_area *fa)
{
return fa->fa_id;
}
static inline uint8_t flash_area_get_device_id(const struct flash_area *fa)
{
return fa->fa_device_id;
}
static inline uint32_t flash_area_get_off(const struct flash_area *fa)
{
return fa->fa_off;
}
static inline uint32_t flash_area_get_size(const struct flash_area *fa)
{
return fa->fa_size;
}
/**
* @brief Structure describing a sector within a flash area.
*
* Each sector has an offset relative to the start of its flash area
* (NOT relative to the start of its flash device), and a size. A
* flash area may contain sectors with different sizes.
*/
struct flash_sector {
/**
* Offset of this sector, from the start of its flash area (not device).
*/
uint32_t fs_off;
/**
* Size of this sector, in bytes.
*/
uint32_t fs_size;
};
static inline uint32_t flash_sector_get_off(const struct flash_sector *fs)
{
return fs->fs_off;
}
static inline uint32_t flash_sector_get_size(const struct flash_sector *fs)
{
return fs->fs_size;
}
struct flash_map_entry {
uint32_t magic;
struct flash_area area;
unsigned int ref_count;
};
/*
* Retrieve a memory-mapped flash device's base address.
* On success, the address will be stored in the value pointed to by
* ret.
* Returns 0 on success, or an error code on failure.
*/
int flash_device_base(uint8_t fd_id, uintptr_t *ret);
/*< Opens the area for use. id is one of the `fa_id`s */
int flash_area_open(uint8_t id, const struct flash_area **);
void flash_area_close(const struct flash_area *);
/*< Reads `len` bytes of flash memory at `off` to the buffer at `dst` */
int flash_area_read(const struct flash_area *, uint32_t off, void *dst,
uint32_t len);
/*< Writes `len` bytes of flash memory at `off` from the buffer at `src` */
int flash_area_write(const struct flash_area *, uint32_t off,
const void *src, uint32_t len);
/*< Erases `len` bytes of flash memory at `off` */
int flash_area_erase(const struct flash_area *, uint32_t off, uint32_t len);
/*< Returns this `flash_area`s alignment */
uint32_t flash_area_align(const struct flash_area *);
/*< Initializes an array of flash_area elements for the slot's sectors */
int flash_area_to_sectors(int idx, int *cnt, struct flash_area *ret);
/*< Returns the `fa_id` for slot, where slot is 0 (primary) or 1 (secondary) */
int flash_area_id_from_image_slot(int slot);
int flash_area_id_from_multi_image_slot(int image_index, int slot);
int flash_area_id_to_multi_image_slot(int image_index, int area_id);
#ifdef MCUBOOT_USE_FLASH_AREA_GET_SECTORS
int flash_area_get_sectors(int idx, uint32_t *cnt, struct flash_sector *ret);
#endif
/*
* Returns the value expected to be read when accesing any erased
* flash byte.
*/
uint8_t flash_area_erased_val(const struct flash_area *fap);
/*
* Reads len bytes from off, and checks if the read data is erased.
*
* Returns 1 if erased, 0 if non-erased, and -1 on failure.
*/
int flash_area_read_is_empty(const struct flash_area *fa, uint32_t off,
void *dst, uint32_t len);
#endif /* __FLASH_MAP_BACKEND_H__ */

48
bootloader/mcuboot/boot/cypress/host.mk Normal file
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################################################################################
# \file host.mk
# \version 1.0
#
# \brief
# Makefile to describe host environment for Cypress MCUBoot based applications.
#
################################################################################
# \copyright
# Copyright 2018-2021 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
################################################################################
# Detect host OS to make resolving compiler pathes easier
UNAME_S := $(shell uname -s)
ifeq ($(UNAME_S), Darwin)
HOST_OS = osx
else
ifeq ($(UNAME_S), Linux)
HOST_OS = linux
else
HOST_OS = win
endif
endif
ifeq ($(HOST_OS), win)
define get_os_path
$(shell cygpath -m $(1))
endef
else
define get_os_path
$(1)
endef
endif
PRJ_DIR=$(call get_os_path, $(CURDIR))

5
bootloader/mcuboot/boot/cypress/keys/cypress-test-ec-p256.pem Normal file
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-----BEGIN PRIVATE KEY-----
MIGHAgEAMBMGByqGSM49AgEGCCqGSM49AwEHBG0wawIBAQQguR/Jq6LjMgp8DVtE
7pKguttNo6L239aEcijzGOr5C72hRANCAAT/NroNASdTGo6bS8r0+C+30YcG0WLV
chWs+99DnOr3SZoalv6/pCNIVrwFv3KkJsmsZUbNNmxeMPr+IlfGGPg0
-----END PRIVATE KEY-----

16
bootloader/mcuboot/boot/cypress/keys/cypress-test-ec-p256.pub Normal file
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@@ -0,0 +1,16 @@
/* Autogenerated by imgtool.py, do not edit. */
const unsigned char ecdsa_pub_key[] = {
0x30, 0x59, 0x30, 0x13, 0x06, 0x07, 0x2a, 0x86,
0x48, 0xce, 0x3d, 0x02, 0x01, 0x06, 0x08, 0x2a,
0x86, 0x48, 0xce, 0x3d, 0x03, 0x01, 0x07, 0x03,
0x42, 0x00, 0x04, 0xff, 0x36, 0xba, 0x0d, 0x01,
0x27, 0x53, 0x1a, 0x8e, 0x9b, 0x4b, 0xca, 0xf4,
0xf8, 0x2f, 0xb7, 0xd1, 0x87, 0x06, 0xd1, 0x62,
0xd5, 0x72, 0x15, 0xac, 0xfb, 0xdf, 0x43, 0x9c,
0xea, 0xf7, 0x49, 0x9a, 0x1a, 0x96, 0xfe, 0xbf,
0xa4, 0x23, 0x48, 0x56, 0xbc, 0x05, 0xbf, 0x72,
0xa4, 0x26, 0xc9, 0xac, 0x65, 0x46, 0xcd, 0x36,
0x6c, 0x5e, 0x30, 0xfa, 0xfe, 0x22, 0x57, 0xc6,
0x18, 0xf8, 0x34,
};
const unsigned int ecdsa_pub_key_len = 91;

270
bootloader/mcuboot/boot/cypress/libs/retarget_io_pdl/cy_retarget_io_pdl.c Normal file
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/***************************************************************************//**
* \file cy_retarget_io.c
*
* \brief
* Provides APIs for retargeting stdio to UART hardware contained on the Cypress
* kits.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cy_retarget_io_pdl.h"
#include "cycfg_peripherals.h"
#include "cy_sysint.h"
#include "cy_scb_uart.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* Tracks the previous character sent to output stream */
#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
static char cy_retarget_io_stdout_prev_char = 0;
#endif /* CY_RETARGET_IO_CONVERT_LF_TO_CRLF */
cy_stc_scb_uart_context_t CYBSP_UART_context;
static uint8_t cy_retarget_io_getchar(void);
static void cy_retarget_io_putchar(char c);
#if defined(__ARMCC_VERSION) /* ARM-MDK */
/***************************************************************************
* Function Name: fputc
***************************************************************************/
__attribute__((weak)) int fputc(int ch, FILE *f)
{
(void)f;
#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
if ((char)ch == '\n' && cy_retarget_io_stdout_prev_char != '\r')
{
cy_retarget_io_putchar('\r');
}
cy_retarget_io_stdout_prev_char = (char)ch;
#endif /* CY_RETARGET_IO_CONVERT_LF_TO_CRLF */
cy_retarget_io_putchar(ch);
return (ch);
}
#elif defined (__ICCARM__) /* IAR */
#include <yfuns.h>
/***************************************************************************
* Function Name: __write
***************************************************************************/
__weak size_t __write(int handle, const unsigned char * buffer, size_t size)
{
size_t nChars = 0;
/* This template only writes to "standard out", for all other file
* handles it returns failure. */
if (handle != _LLIO_STDOUT)
{
return (_LLIO_ERROR);
}
if (buffer != NULL)
{
for (/* Empty */; nChars < size; ++nChars)
{
#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
if (*buffer == '\n' && cy_retarget_io_stdout_prev_char != '\r')
{
cy_retarget_io_putchar('\r');
}
cy_retarget_io_stdout_prev_char = *buffer;
#endif /* CY_RETARGET_IO_CONVERT_LF_TO_CRLF */
cy_retarget_io_putchar(*buffer);
++buffer;
}
}
return (nChars);
}
#else /* (__GNUC__) GCC */
/* Add an explicit reference to the floating point printf library to allow
the usage of floating point conversion specifier. */
__asm (".global _printf_float");
/***************************************************************************
* Function Name: _write
***************************************************************************/
__attribute__((weak)) int _write (int fd, const char *ptr, int len)
{
int nChars = 0;
(void)fd;
if (ptr != NULL)
{
for (/* Empty */; nChars < len; ++nChars)
{
#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
if (*ptr == '\n' && cy_retarget_io_stdout_prev_char != '\r')
{
cy_retarget_io_putchar('\r');
}
cy_retarget_io_stdout_prev_char = *ptr;
#endif /* CY_RETARGET_IO_CONVERT_LF_TO_CRLF */
cy_retarget_io_putchar((uint32_t)*ptr);
++ptr;
}
}
return (nChars);
}
#endif
#if defined(__ARMCC_VERSION) /* ARM-MDK */
/***************************************************************************
* Function Name: fgetc
***************************************************************************/
__attribute__((weak)) int fgetc(FILE *f)
{
(void)f;
return (cy_retarget_io_getchar());
}
#elif defined (__ICCARM__) /* IAR */
__weak size_t __read(int handle, unsigned char * buffer, size_t size)
{
/* This template only reads from "standard in", for all other file
handles it returns failure. */
if ((handle != _LLIO_STDIN) || (buffer == NULL))
{
return (_LLIO_ERROR);
}
else
{
*buffer = cy_retarget_io_getchar();
return (1);
}
}
#else /* (__GNUC__) GCC */
/* Add an explicit reference to the floating point scanf library to allow
the usage of floating point conversion specifier. */
__asm (".global _scanf_float");
__attribute__((weak)) int _read (int fd, char *ptr, int len)
{
int nChars = 0;
(void)fd;
if (ptr != NULL)
{
for(/* Empty */;nChars < len;++ptr)
{
*ptr = (char)cy_retarget_io_getchar();
++nChars;
if((*ptr == '\n') || (*ptr == '\r'))
{
break;
}
}
}
return (nChars);
}
#endif
static uint8_t cy_retarget_io_getchar(void)
{
uint32_t read_value = Cy_SCB_UART_Get(CYBSP_UART_HW);
while (read_value == CY_SCB_UART_RX_NO_DATA)
{
read_value = Cy_SCB_UART_Get(CYBSP_UART_HW);
}
return (uint8_t)read_value;
}
static void cy_retarget_io_putchar(char c)
{
uint32_t count = 0;
while (count == 0)
{
count = Cy_SCB_UART_Put(CYBSP_UART_HW, c);
}
}
static cy_rslt_t cy_retarget_io_pdl_setbaud(CySCB_Type *base, uint32_t baudrate)
{
cy_rslt_t result = CY_RSLT_TYPE_ERROR;
uint8_t oversample_value = 8u;
uint8_t frac_bits = 0u;
uint32_t divider;
Cy_SCB_UART_Disable(base, NULL);
result = (cy_rslt_t) Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0);
divider = ((Cy_SysClk_ClkPeriGetFrequency() * (1 << frac_bits)) + ((baudrate * oversample_value) / 2)) / (baudrate * oversample_value) - 1;
if (result == CY_RSLT_SUCCESS)
{
result = (cy_rslt_t) Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0u, divider);
}
if (result == CY_RSLT_SUCCESS)
{
result = Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0u);
}
Cy_SCB_UART_Enable(base);
return result;
}
cy_rslt_t cy_retarget_io_pdl_init(uint32_t baudrate)
{
cy_rslt_t result = CY_RSLT_TYPE_ERROR;
result = (cy_rslt_t)Cy_SCB_UART_Init(CYBSP_UART_HW, &CYBSP_UART_config, &CYBSP_UART_context);
if (result == CY_RSLT_SUCCESS)
{
result = cy_retarget_io_pdl_setbaud(CYBSP_UART_HW, baudrate);
}
if (result == CY_RSLT_SUCCESS)
{
Cy_SCB_UART_Enable(CYBSP_UART_HW);
}
return result;
}
/**
* @brief Wait while UART completes transfer. Try for tries_count times -
* once each 10 millisecons.
*/
void cy_retarget_io_wait_tx_complete(CySCB_Type *base, uint32_t tries_count)
{
while(tries_count > 0)
{
if (!Cy_SCB_UART_IsTxComplete(base)) {
Cy_SysLib_DelayCycles(10 * cy_delayFreqKhz);
tries_count -= 1;
} else {
return;
}
}
}
void cy_retarget_io_pdl_deinit()
{
Cy_SCB_UART_DeInit(CYBSP_UART_HW);
}
#if defined(__cplusplus)
}
#endif

62
bootloader/mcuboot/boot/cypress/libs/retarget_io_pdl/cy_retarget_io_pdl.h Normal file
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/***************************************************************************//**
* \file cy_retarget_io.h
*
* \brief
* Provides APIs for transmitting messages to or from the board via standard
* printf/scanf functions. Messages are transmitted over a UART connection which
* is generally connected to a host machine. Transmission is done at 115200 baud
* using the tx and rx pins provided by the user of this library. The UART
* instance is made available via cy_retarget_io_uart_obj in case any changes
* to the default configuration are desired.
* NOTE: If the application is built using newlib-nano, by default, floating
* point format strings (%f) are not supported. To enable this support you must
* add '-u _printf_float' to the linker command line.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#pragma once
#include <stdio.h>
#include "cy_result.h"
#include "cy_pdl.h"
#if defined(__cplusplus)
extern "C" {
#endif
/** UART baud rate */
#define CY_RETARGET_IO_BAUDRATE (115200)
/** Defining this macro enables conversion of line feed (LF) into carriage
* return followed by line feed (CR & LF) on the output direction (STDOUT). You
* can define this macro through the DEFINES variable in the application
* Makefile.
*/
#define CY_RETARGET_IO_CONVERT_LF_TO_CRLF
cy_rslt_t cy_retarget_io_pdl_init(uint32_t baudrate);
void cy_retarget_io_wait_tx_complete(CySCB_Type *base, uint32_t tries_count);
void cy_retarget_io_pdl_deinit(void);
#if defined(__cplusplus)
}
#endif

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/***************************************************************************//**
* \file cy_wdg.c
*
* \brief
* Provides a high level interface for interacting with the Cypress Watchdog Timer.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
*
********************************************************************************
* \copyright
* Copyright 2019-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include <stdbool.h>
#include "watchdog.h"
#include "cy_wdt.h"
#include "cy_utils.h"
#if defined(__cplusplus)
extern "C" {
#endif
#if defined(COMPONENT_PSOC6)
#define _cy_wdg_lock() Cy_WDT_Lock()
#define _cy_wdg_unlock() Cy_WDT_Unlock()
#else
#define _cy_wdg_lock()
#define _cy_wdg_unlock()
#endif
// ((2^16 * 2) + (2^16 - 1)) * .030518 ms
/** Maximum WDT timeout in milliseconds */
#define _cy_wdg_MAX_TIMEOUT_MS 6000
/** Maximum number of ignore bits */
#define _cy_wdg_MAX_IGNORE_BITS 12
typedef struct {
uint16_t min_period_ms; // Minimum period in milliseconds that can be represented with this many ignored bits
uint16_t round_threshold_ms; // Timeout threshold in milliseconds from which to round up to the minimum period
} _cy_wdg_ignore_bits_data_t;
// ILO Frequency = 32768 Hz
// ILO Period = 1 / 32768 Hz = .030518 ms
// WDT Reset Period (timeout_ms) = .030518 ms * (2 * 2^(16 - ignore_bits) + match)
// ignore_bits range: 0 - 12
// match range: 0 - (2^(16 - ignore_bits) - 1)
static const _cy_wdg_ignore_bits_data_t _cy_wdg_ignore_data[] = {
{4001, 3001}, // 0 bits: min period: 4001ms, max period: 6000ms, round up from 3001+ms
{2001, 1500}, // 1 bit: min period: 2001ms, max period: 3000ms, round up from 1500+ms
{1001, 750}, // 2 bits: min period: 1001ms, max period: 1499ms, round up from 750+ms
{501, 375}, // 3 bits: min period: 501ms, max period: 749ms, round up from 375+ms
{251, 188}, // 4 bits: min period: 251ms, max period: 374ms, round up from 188+ms
{126, 94}, // 5 bits: min period: 126ms, max period: 187ms, round up from 94+ms
{63, 47}, // 6 bits: min period: 63ms, max period: 93ms, round up from 47+ms
{32, 24}, // 7 bits: min period: 32ms, max period: 46ms, round up from 24+ms
{16, 12}, // 8 bits: min period: 16ms, max period: 23ms, round up from 12+ms
{8, 6}, // 9 bits: min period: 8ms, max period: 11ms, round up from 6+ms
{4, 3}, // 10 bits: min period: 4ms, max period: 5ms, round up from 3+ms
{2, 2}, // 11 bits: min period: 2ms, max period: 2ms
{1, 1} // 12 bits: min period: 1ms, max period: 1ms
};
static bool _cy_wdg_initialized = false;
static bool _cy_wdg_pdl_initialized = false;
static uint16_t _cy_wdg_initial_timeout_ms = 0;
static uint8_t _cy_wdg_initial_ignore_bits = 0;
static __INLINE uint32_t _cy_wdg_timeout_to_ignore_bits(uint32_t *timeout_ms) {
for (uint32_t i = 0; i <= _cy_wdg_MAX_IGNORE_BITS; i++)
{
if (*timeout_ms >= _cy_wdg_ignore_data[i].round_threshold_ms)
{
if (*timeout_ms < _cy_wdg_ignore_data[i].min_period_ms)
*timeout_ms = _cy_wdg_ignore_data[i].min_period_ms;
return i;
}
}
return _cy_wdg_MAX_IGNORE_BITS; // Should never reach this
}
static __INLINE uint16_t _cy_wdg_timeout_to_match(uint16_t timeout_ms, uint16_t ignore_bits)
{
// match = (timeout_ms / .030518 ms) - (2 * 2^(16 - ignore_bits))
return (uint16_t)(timeout_ms / .030518) - (1UL << (17 - ignore_bits)) + Cy_WDT_GetCount();
}
/* Start API implementing */
cy_rslt_t cy_wdg_init(uint32_t timeout_ms)
{
if (timeout_ms == 0 || timeout_ms > _cy_wdg_MAX_TIMEOUT_MS)
{
return -1;
}
if (_cy_wdg_initialized)
{
return -1;
}
_cy_wdg_initialized = true;
if (!_cy_wdg_pdl_initialized)
{
Cy_WDT_Enable();
Cy_WDT_MaskInterrupt();
_cy_wdg_pdl_initialized = true;
}
cy_wdg_stop();
_cy_wdg_initial_timeout_ms = timeout_ms;
uint8_t ignore_bits = _cy_wdg_timeout_to_ignore_bits(&timeout_ms);
_cy_wdg_initial_ignore_bits = ignore_bits;
Cy_WDT_SetIgnoreBits(ignore_bits);
Cy_WDT_SetMatch(_cy_wdg_timeout_to_match(timeout_ms, ignore_bits));
cy_wdg_start();
return CY_RSLT_SUCCESS;
}
void cy_wdg_free()
{
cy_wdg_stop();
_cy_wdg_initialized = false;
}
void cy_wdg_kick()
{
/* Clear to prevent reset from WDT */
Cy_WDT_ClearWatchdog();
_cy_wdg_unlock();
Cy_WDT_SetMatch(_cy_wdg_timeout_to_match(_cy_wdg_initial_timeout_ms, _cy_wdg_initial_ignore_bits));
_cy_wdg_lock();
}
void cy_wdg_start()
{
_cy_wdg_unlock();
Cy_WDT_Enable();
_cy_wdg_lock();
}
void cy_wdg_stop()
{
_cy_wdg_unlock();
Cy_WDT_Disable();
}
uint32_t cy_wdg_get_timeout_ms()
{
return _cy_wdg_initial_timeout_ms;
}
uint32_t cy_wdg_get_max_timeout_ms(void)
{
return _cy_wdg_MAX_TIMEOUT_MS;
}
#if defined(__cplusplus)
}
#endif

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/***************************************************************************//**
* \file cy_wdg.h
*
* \brief
* Provides a high level interface for interacting with the Watchdog Timer.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2019-2020 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#pragma once
#if defined(__cplusplus)
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
/** Initialize and start the WDT
*
* The specified timeout must be at least 1ms and at most the WDT's maximum timeout (see cy_wdg_get_max_timeout_ms()).
* @param[inout] timeout_ms The time in milliseconds before the WDT times out (1ms - max) (see cy_wdg_get_max_timeout_ms())
* @return The status of the init request
*
* Returns CY_RSLT_SUCCESS if the operation was successfull.
*/
cy_rslt_t cy_wdg_init(uint32_t timeout_ms);
/** Free the WDT
*
* Powers down the WDT.
* After calling this function no other WDT functions should be called except
* cy_wdg_init().
*/
void cy_wdg_free();
/** Resets the WDT
*
* This function should be called periodically to prevent the WDT from timing out and resetting the device.
*/
void cy_wdg_kick();
/** Start (enable) the WDT
*
* @return The status of the start request
*/
void cy_wdg_start();
/** Stop (disable) the WDT
*
* @return The status of the stop request
*/
void cy_wdg_stop();
/** Get the WDT timeout
*
* Gets the time in milliseconds before the WDT times out.
* @return The time in milliseconds before the WDT times out
*/
uint32_t cy_wdg_get_timeout_ms();
/** Gets the maximum WDT timeout in milliseconds
*
* @return The maximum timeout for the WDT
*/
uint32_t cy_wdg_get_max_timeout_ms(void);
#if defined(__cplusplus)
}
#endif

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bootloader/mcuboot/boot/cypress/platforms.mk Normal file
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################################################################################
# \file platforms.mk
# \version 1.0
#
# \brief
# Makefile to describe supported boards and platforms for Cypress MCUBoot based applications.
#
################################################################################
# \copyright
# Copyright 2018-2019 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
################################################################################
include host.mk
# Target platform is built for. PSOC_062_2M is set by default
# Supported:
# - PSOC_062_2M
# - PSOC_062_1M
# - PSOC_062_512K
# default PLATFORM
PLATFORM ?= PSOC_062_2M
# supported platforms
PLATFORMS := PSOC_062_2M PSOC_062_1M PSOC_062_512K
ifneq ($(filter $(PLATFORM), $(PLATFORMS)),)
else
$(error Not supported platform: '$(PLATFORM)')
endif
# For which core this application is built
CORE ?= CM0P
# MCU device selection, based on target device.
# Default chips are used for supported platforms
# This can be redefined in case of other chip usage
ifeq ($(PLATFORM), PSOC_062_2M)
# base kit CY8CPROTO-062-4343W
DEVICE ?= CY8C624ABZI-D44
PLATFORM_SUFFIX := 02
else ifeq ($(PLATFORM), PSOC_062_1M)
# base kit CY8CKIT-062-WIFI-BT
DEVICE ?= CY8C6247BZI-D54
PLATFORM_SUFFIX := 01
else ifeq ($(PLATFORM), PSOC_062_512K)
# base kit CY8CPROTO-062S3-4343W
DEVICE ?= CY8C6245LQI-S3D72
PLATFORM_SUFFIX := 03
endif
# Add device name to defines
DEFINES += $(DEVICE)
DEFINES += $(PLATFORM)
# Convert defines to regular -DMY_NAME style
ifneq ($(DEFINES),)
DEFINES_PLATFORM :=$(addprefix -D, $(subst -,_,$(DEFINES)))
endif
ifeq ($(MAKEINFO) , 1)
$(info $(PLATFORM_SUFFIX))
$(info $(DEVICE))
$(info $(DEFINES_PLATFORM))
endif

418
bootloader/mcuboot/boot/cypress/platforms/PSOC_062_2M/CM0P/GCC_ARM/cy8c6xxa_cm0plus.ld Normal file
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/***************************************************************************//**
* \file cy8c6xxa_cm0plus.ld
* \version 2.70
*
* Linker file for the GNU C compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point location is fixed and starts at 0x10000000. The valid
* application image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* The size of the stack section at the end of CM0+ SRAM */
STACK_SIZE = 0x1000;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
* EXTERN multiple times. This command has the same effect as the -u command-line
* option.
*/
EXTERN(Reset_Handler)
/* The MEMORY section below describes the location and size of blocks of memory in the target.
* Use this section to specify the memory regions available for allocation.
*/
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
* You can change the memory allocation by editing the 'ram' and 'flash' regions.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'.
*/
ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000
flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
/* The following regions define device specific memory regions and must not be changed. */
sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
SECTIONS
{
.cy_app_header :
{
KEEP(*(.cy_app_header))
} > flash
/* Cortex-M0+ application flash area */
.text :
{
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))
. = ALIGN(4);
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
/* Read-only code (constants). */
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.eh_frame*))
} > flash
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > flash
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > flash
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy interrupt vectors from flash to RAM */
LONG (__Vectors) /* From */
LONG (__ram_vectors_start__) /* To */
LONG (__Vectors_End - __Vectors) /* Size */
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG (__data_end__ - __data_start__) /* Size */
__copy_table_end__ = .;
} > flash
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm0plus.S */
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > flash
__etext = . ;
.ramVectors (NOLOAD) : ALIGN(8)
{
__ram_vectors_start__ = .;
KEEP(*(.ram_vectors))
__ram_vectors_end__ = .;
} > ram
.data __ram_vectors_end__ : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
KEEP(*(.cy_ramfunc*))
. = ALIGN(4);
__data_end__ = .;
} > ram
/* Place variables in the section that should not be initialized during the
* device startup.
*/
.noinit (NOLOAD) : ALIGN(8)
{
KEEP(*(.noinit))
} > ram
/* The uninitialized global or static variables are placed in this section.
*
* The NOLOAD attribute tells linker that .bss section does not consume
* any space in the image. The NOLOAD attribute changes the .bss type to
* NOBITS, and that makes linker to A) not allocate section in memory, and
* A) put information to clear the section with all zeros during application
* loading.
*
* Without the NOLOAD attribute, the .bss section might get PROGBITS type.
* This makes linker to A) allocate zeroed section in memory, and B) copy
* this section to RAM during application loading.
*/
.bss (NOLOAD):
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram
.heap (NOLOAD):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
__HeapLimit = .;
} > ram
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
KEEP(*(.stack*))
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Emulated EEPROM Flash area */
.cy_em_eeprom :
{
KEEP(*(.cy_em_eeprom))
} > em_eeprom
/* Supervisory Flash: User data */
.cy_sflash_user_data :
{
KEEP(*(.cy_sflash_user_data))
} > sflash_user_data
/* Supervisory Flash: Normal Access Restrictions (NAR) */
.cy_sflash_nar :
{
KEEP(*(.cy_sflash_nar))
} > sflash_nar
/* Supervisory Flash: Public Key */
.cy_sflash_public_key :
{
KEEP(*(.cy_sflash_public_key))
} > sflash_public_key
/* Supervisory Flash: Table of Content # 2 */
.cy_toc_part2 :
{
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
/* Supervisory Flash: Table of Content # 2 Copy */
.cy_rtoc_part2 :
{
KEEP(*(.cy_rtoc_part2))
} > sflash_rtoc_2
/* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details.
*/
.cy_xip :
{
KEEP(*(.cy_xip))
} > xip
/* eFuse */
.cy_efuse :
{
KEEP(*(.cy_efuse))
} > efuse
/* These sections are used for additional metadata (silicon revision,
* Silicon/JTAG ID, etc.) storage.
*/
.cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
}
/* The following symbols used by the cymcuelftool. */
/* Flash */
__cy_memory_0_start = 0x10000000;
__cy_memory_0_length = 0x00200000;
__cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
__cy_memory_1_start = 0x14000000;
__cy_memory_1_length = 0x8000;
__cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
__cy_memory_2_start = 0x16000000;
__cy_memory_2_length = 0x8000;
__cy_memory_2_row_size = 0x200;
/* XIP */
__cy_memory_3_start = 0x18000000;
__cy_memory_3_length = 0x08000000;
__cy_memory_3_row_size = 0x200;
/* eFuse */
__cy_memory_4_start = 0x90700000;
__cy_memory_4_length = 0x100000;
__cy_memory_4_row_size = 1;
/* EOF */

372
bootloader/mcuboot/boot/cypress/platforms/PSOC_062_2M/CM0P/GCC_ARM/startup_psoc6_02_cm0plus.S Normal file
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/**************************************************************************//**
* @file startup_psoc6_02_cm0plus.S
* @brief CMSIS Core Device Startup File for
* ARMCM0plus Device Series
* @version V5.00
* @date 02. March 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Address of the NMI handler */
#define CY_NMI_HANLDER_ADDR 0x0000000D
/* The CPU VTOR register */
#define CY_CPU_VTOR_ADDR 0xE000ED08
/* Copy flash vectors and data section to RAM */
#define __STARTUP_COPY_MULTIPLE
/* Clear single BSS section */
#define __STARTUP_CLEAR_BSS
.syntax unified
.arch armv6-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00001000
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000400
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long CY_NMI_HANLDER_ADDR /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts Description */
.long NvicMux0_IRQHandler /* CPU User Interrupt #0 */
.long NvicMux1_IRQHandler /* CPU User Interrupt #1 */
.long NvicMux2_IRQHandler /* CPU User Interrupt #2 */
.long NvicMux3_IRQHandler /* CPU User Interrupt #3 */
.long NvicMux4_IRQHandler /* CPU User Interrupt #4 */
.long NvicMux5_IRQHandler /* CPU User Interrupt #5 */
.long NvicMux6_IRQHandler /* CPU User Interrupt #6 */
.long NvicMux7_IRQHandler /* CPU User Interrupt #7 */
.long Internal0_IRQHandler /* Internal SW Interrupt #0 */
.long Internal1_IRQHandler /* Internal SW Interrupt #1 */
.long Internal2_IRQHandler /* Internal SW Interrupt #2 */
.long Internal3_IRQHandler /* Internal SW Interrupt #3 */
.long Internal4_IRQHandler /* Internal SW Interrupt #4 */
.long Internal5_IRQHandler /* Internal SW Interrupt #5 */
.long Internal6_IRQHandler /* Internal SW Interrupt #6 */
.long Internal7_IRQHandler /* Internal SW Interrupt #7 */
.size __Vectors, . - __Vectors
.equ __VectorsSize, . - __Vectors
.section .ram_vectors
.align 2
.globl __ramVectors
__ramVectors:
.space __VectorsSize
.size __ramVectors, . - __ramVectors
.text
.thumb
.thumb_func
.align 2
/*
* Device startup customization
*
* Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
* because this function is executed as the first instruction in the ResetHandler.
* The PDL is also not initialized to use the proper register offsets.
* The user of this function is responsible for initializing the PDL and resources before using them.
*/
.weak Cy_OnResetUser
.func Cy_OnResetUser, Cy_OnResetUser
.type Cy_OnResetUser, %function
Cy_OnResetUser:
bx lr
.size Cy_OnResetUser, . - Cy_OnResetUser
.endfunc
/* Reset handler */
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
bl Cy_OnResetUser
cpsid i
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
blt .L_loop0_0_done
ldr r0, [r1, r3]
str r0, [r2, r3]
b .L_loop0_0
.L_loop0_0_done:
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .L_loop1_done
.L_loop1:
subs r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .L_loop1
.L_loop1_done:
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
blt .L_loop2_0_done
str r0, [r1, r2]
b .L_loop2_0
.L_loop2_0_done:
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
subs r2, r1
ble .L_loop3_done
.L_loop3:
subs r2, #4
str r0, [r1, r2]
bgt .L_loop3
.L_loop3_done:
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
/* Update Vector Table Offset Register. */
ldr r0, =__ramVectors
ldr r1, =CY_CPU_VTOR_ADDR
str r0, [r1]
dsb 0xF
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
bl main
/* Should never get here */
b .
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
.weak Cy_SysLib_FaultHandler
.type Cy_SysLib_FaultHandler, %function
Cy_SysLib_FaultHandler:
b .
.size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
.type Fault_Handler, %function
Fault_Handler:
/* Storing LR content for Creator call stack trace */
push {LR}
movs r0, #4
mov r1, LR
tst r0, r1
beq .L_MSP
mrs r0, PSP
b .L_API_call
.L_MSP:
mrs r0, MSP
.L_API_call:
/* Compensation of stack pointer address due to pushing 4 bytes of LR */
adds r0, r0, #4
bl Cy_SysLib_FaultHandler
b .
.size Fault_Handler, . - Fault_Handler
.macro def_fault_Handler fault_handler_name
.weak \fault_handler_name
.set \fault_handler_name, Fault_Handler
.endm
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_fault_Handler HardFault_Handler
def_irq_handler SVC_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */
def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */
def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */
def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */
def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */
def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */
def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */
def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */
def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */
def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */
def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */
def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */
def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */
def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */
def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */
def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */
.end
/* [] END OF FILE */

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bootloader/mcuboot/boot/cypress/platforms/PSOC_062_2M/CM4/GCC_ARM/cy8c6xxa_cm4_dual.ld Normal file
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/***************************************************************************//**
* \file cy8c6xxa_cm4_dual.ld
* \version 2.70
*
* Linker file for the GNU C compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point location is fixed and starts at 0x10000000. The valid
* application image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* The size of the stack section at the end of CM4 SRAM */
STACK_SIZE = 0x1000;
/* The size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
* EXTERN multiple times. This command has the same effect as the -u command-line
* option.
*/
EXTERN(Reset_Handler)
/* The MEMORY section below describes the location and size of blocks of memory in the target.
* Use this section to specify the memory regions available for allocation.
*/
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing the 'ram' and 'flash' regions.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
*/
ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0xFD800
flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x200000
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
/* The following regions define device specific memory regions and must not be changed. */
sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
SECTIONS
{
/* Cortex-M0+ application flash image area */
.cy_m0p_image ORIGIN(flash) :
{
. = ALIGN(4);
__cy_m0p_code_start = . ;
KEEP(*(.cy_m0p_image))
__cy_m0p_code_end = . ;
} > flash
/* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */
ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE")
/* Cortex-M4 application flash area */
.text ORIGIN(flash) + FLASH_CM0P_SIZE :
{
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))
. = ALIGN(4);
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
/* Read-only code (constants). */
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.eh_frame*))
} > flash
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > flash
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > flash
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy interrupt vectors from flash to RAM */
LONG (__Vectors) /* From */
LONG (__ram_vectors_start__) /* To */
LONG (__Vectors_End - __Vectors) /* Size */
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG (__data_end__ - __data_start__) /* Size */
__copy_table_end__ = .;
} > flash
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > flash
__etext = . ;
.ramVectors (NOLOAD) : ALIGN(8)
{
__ram_vectors_start__ = .;
KEEP(*(.ram_vectors))
__ram_vectors_end__ = .;
} > ram
.data __ram_vectors_end__ : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
KEEP(*(.cy_ramfunc*))
. = ALIGN(4);
__data_end__ = .;
} > ram
/* Place variables in the section that should not be initialized during the
* device startup.
*/
.noinit (NOLOAD) : ALIGN(8)
{
KEEP(*(.noinit))
} > ram
/* The uninitialized global or static variables are placed in this section.
*
* The NOLOAD attribute tells linker that .bss section does not consume
* any space in the image. The NOLOAD attribute changes the .bss type to
* NOBITS, and that makes linker to A) not allocate section in memory, and
* A) put information to clear the section with all zeros during application
* loading.
*
* Without the NOLOAD attribute, the .bss section might get PROGBITS type.
* This makes linker to A) allocate zeroed section in memory, and B) copy
* this section to RAM during application loading.
*/
.bss (NOLOAD):
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram
.heap (NOLOAD):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
__HeapLimit = .;
} > ram
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
KEEP(*(.stack*))
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Used for the digital signature of the secure application and the Bootloader SDK application.
* The size of the section depends on the required data size. */
.cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
{
KEEP(*(.cy_app_signature))
} > flash
/* Emulated EEPROM Flash area */
.cy_em_eeprom :
{
KEEP(*(.cy_em_eeprom))
} > em_eeprom
/* Supervisory Flash: User data */
.cy_sflash_user_data :
{
KEEP(*(.cy_sflash_user_data))
} > sflash_user_data
/* Supervisory Flash: Normal Access Restrictions (NAR) */
.cy_sflash_nar :
{
KEEP(*(.cy_sflash_nar))
} > sflash_nar
/* Supervisory Flash: Public Key */
.cy_sflash_public_key :
{
KEEP(*(.cy_sflash_public_key))
} > sflash_public_key
/* Supervisory Flash: Table of Content # 2 */
.cy_toc_part2 :
{
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
/* Supervisory Flash: Table of Content # 2 Copy */
.cy_rtoc_part2 :
{
KEEP(*(.cy_rtoc_part2))
} > sflash_rtoc_2
/* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details.
*/
.cy_xip :
{
KEEP(*(.cy_xip))
} > xip
/* eFuse */
.cy_efuse :
{
KEEP(*(.cy_efuse))
} > efuse
/* These sections are used for additional metadata (silicon revision,
* Silicon/JTAG ID, etc.) storage.
*/
.cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
}
/* The following symbols used by the cymcuelftool. */
/* Flash */
__cy_memory_0_start = 0x10000000;
__cy_memory_0_length = 0x00200000;
__cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
__cy_memory_1_start = 0x14000000;
__cy_memory_1_length = 0x8000;
__cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
__cy_memory_2_start = 0x16000000;
__cy_memory_2_length = 0x8000;
__cy_memory_2_row_size = 0x200;
/* XIP */
__cy_memory_3_start = 0x18000000;
__cy_memory_3_length = 0x08000000;
__cy_memory_3_row_size = 0x200;
/* eFuse */
__cy_memory_4_start = 0x90700000;
__cy_memory_4_length = 0x100000;
__cy_memory_4_row_size = 1;
/* EOF */

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bootloader/mcuboot/boot/cypress/platforms/PSOC_062_2M/CM4/GCC_ARM/startup_psoc6_02_cm4.S Normal file
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/**************************************************************************//**
* @file startup_psoc6_02_cm4.S
* @brief CMSIS Core Device Startup File for
* ARMCM4 Device Series
* @version V5.00
* @date 02. March 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Address of the NMI handler */
#define CY_NMI_HANLDER_ADDR 0x0000000D
/* The CPU VTOR register */
#define CY_CPU_VTOR_ADDR 0xE000ED08
/* Copy flash vectors and data section to RAM */
#define __STARTUP_COPY_MULTIPLE
/* Clear single BSS section */
#define __STARTUP_CLEAR_BSS
.syntax unified
.arch armv7-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00001000
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000400
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long CY_NMI_HANLDER_ADDR /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts Description */
.long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
.long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
.long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
.long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
.long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
.long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
.long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
.long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
.long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
.long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
.long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
.long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
.long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
.long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
.long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
.long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
.long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
.long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
.long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
.long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
.long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
.long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
.long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
.long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
.long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
.long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
.long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
.long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
.long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
.long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
.long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
.long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
.long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
.long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
.long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
.long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
.long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
.long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
.long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
.long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
.long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
.long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
.long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
.long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
.long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
.long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
.long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
.long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */
.long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */
.long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */
.long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */
.long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
.long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
.long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
.long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */
.long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */
.long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
.long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
.long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
.long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
.long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
.long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
.long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
.long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
.long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
.long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
.long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
.long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
.long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
.long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
.long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
.long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
.long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
.long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
.long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
.long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
.long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
.long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
.long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
.long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
.long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
.long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
.long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
.long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
.long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
.long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
.long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
.long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
.long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
.long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
.long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
.long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
.long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
.long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
.long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
.long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
.long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
.long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
.long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
.long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
.long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
.long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
.long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
.long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
.long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
.long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
.long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
.long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
.long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
.long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
.long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
.long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
.long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
.long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
.long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
.long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
.long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
.long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
.long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
.long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
.long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
.long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
.long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
.long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
.long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
.long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
.long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
.long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
.long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
.long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
.long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
.long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
.long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
.long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
.long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
.long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
.long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
.long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
.long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
.long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
.long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
.long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
.long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
.long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
.long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
.long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
.long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
.long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
.long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
.long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
.long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
.long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
.long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
.long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
.long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
.long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
.long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */
.long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */
.long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */
.long profile_interrupt_IRQHandler /* Energy Profiler interrupt */
.long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
.long usb_interrupt_hi_IRQHandler /* USB Interrupt */
.long usb_interrupt_med_IRQHandler /* USB Interrupt */
.long usb_interrupt_lo_IRQHandler /* USB Interrupt */
.long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
.long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
.long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */
.long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
.size __Vectors, . - __Vectors
.equ __VectorsSize, . - __Vectors
.section .ram_vectors
.align 2
.globl __ramVectors
__ramVectors:
.space __VectorsSize
.size __ramVectors, . - __ramVectors
.text
.thumb
.thumb_func
.align 2
/*
* Device startup customization
*
* Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
* because this function is executed as the first instruction in the ResetHandler.
* The PDL is also not initialized to use the proper register offsets.
* The user of this function is responsible for initializing the PDL and resources before using them.
*/
.weak Cy_OnResetUser
.func Cy_OnResetUser, Cy_OnResetUser
.type Cy_OnResetUser, %function
Cy_OnResetUser:
bx lr
.size Cy_OnResetUser, . - Cy_OnResetUser
.endfunc
/* OS-specific low-level initialization */
.weak cy_toolchain_init
.func cy_toolchain_init, cy_toolchain_init
.type cy_toolchain_init, %function
cy_toolchain_init:
bx lr
.size cy_toolchain_init, . - cy_toolchain_init
.endfunc
/* Reset handler */
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
bl Cy_OnResetUser
cpsid i
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
/* Update Vector Table Offset Register. */
ldr r0, =__ramVectors
ldr r1, =CY_CPU_VTOR_ADDR
str r0, [r1]
dsb 0xF
/* Enable the FPU if used */
bl Cy_SystemInitFpuEnable
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
/* OS-specific low-level initialization */
bl cy_toolchain_init
/* Call C/C++ static constructors */
bl __libc_init_array
/* Execute main application */
bl main
/* Call C/C++ static destructors */
bl __libc_fini_array
/* Should never get here */
b .
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
.weak Cy_SysLib_FaultHandler
.type Cy_SysLib_FaultHandler, %function
Cy_SysLib_FaultHandler:
b .
.size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
.type Fault_Handler, %function
Fault_Handler:
/* Storing LR content for Creator call stack trace */
push {LR}
movs r0, #4
mov r1, LR
tst r0, r1
beq .L_MSP
mrs r0, PSP
b .L_API_call
.L_MSP:
mrs r0, MSP
.L_API_call:
/* Compensation of stack pointer address due to pushing 4 bytes of LR */
adds r0, r0, #4
bl Cy_SysLib_FaultHandler
b .
.size Fault_Handler, . - Fault_Handler
.macro def_fault_Handler fault_handler_name
.weak \fault_handler_name
.set \fault_handler_name, Fault_Handler
.endm
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_fault_Handler HardFault_Handler
def_fault_Handler MemManage_Handler
def_fault_Handler BusFault_Handler
def_fault_Handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */
def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */
def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */
def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */
def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */
def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */
def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */
def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */
def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */
def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */
def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */
def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */
def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */
def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */
def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
.end
/* [] END OF FILE */

33
bootloader/mcuboot/boot/cypress/platforms/cycfg.c Normal file
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/*******************************************************************************
* File Name: cycfg.c
*
* Description:
* Wrapper function to initialize all generated code.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg.h"
void init_cycfg_all(void)
{
init_cycfg_system();
init_cycfg_clocks();
}

45
bootloader/mcuboot/boot/cypress/platforms/cycfg.h Normal file
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/*******************************************************************************
* File Name: cycfg.h
*
* Description:
* Simple wrapper header containing all generated files.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_H)
#define CYCFG_H
#if defined(__cplusplus)
extern "C" {
#endif
#include "cycfg_system.h"
#include "cycfg_clocks.h"
void init_cycfg_all(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_H */

47
bootloader/mcuboot/boot/cypress/platforms/cycfg_clocks.c Normal file
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/*******************************************************************************
* File Name: cycfg_clocks.c
*
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_clocks.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_CLK_DIV_HW,
.channel_num = CYBSP_CSD_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void)
{
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
}

54
bootloader/mcuboot/boot/cypress/platforms/cycfg_clocks.h Normal file
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/*******************************************************************************
* File Name: cycfg_clocks.h
*
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_CLOCKS_H)
#define CYCFG_CLOCKS_H
#include "cy_sysclk.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#if defined(__cplusplus)
extern "C" {
#endif
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_CLK_DIV_NUM 0U
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_CLOCKS_H */

73
bootloader/mcuboot/boot/cypress/platforms/cycfg_peripherals.c Normal file
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/*******************************************************************************
* File Name: cycfg_peripherals.c
*
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_peripherals.h"
const cy_stc_scb_uart_config_t CYBSP_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
.smartCardRetryOnNack = false,
.irdaInvertRx = false,
.irdaEnableLowPowerReceiver = false,
.oversample = 8,
.enableMsbFirst = false,
.dataWidth = 8UL,
.parity = CY_SCB_UART_PARITY_NONE,
.stopBits = CY_SCB_UART_STOP_BITS_1,
.enableInputFilter = false,
.breakWidth = 11UL,
.dropOnFrameError = false,
.dropOnParityError = false,
.receiverAddress = 0x0UL,
.receiverAddressMask = 0x0UL,
.acceptAddrInFifo = false,
.enableCts = false,
.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
.rtsRxFifoLevel = 0UL,
.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
.rxFifoTriggerLevel = 0UL,
.rxFifoIntEnableMask = 0UL,
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_UART_obj =
{
.type = CYHAL_RSC_SCB,
.block_num = 5U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void)
{
Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_16_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_UART_obj);
#endif //defined (CY_USING_HAL)
}

57
bootloader/mcuboot/boot/cypress/platforms/cycfg_peripherals.h Normal file
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/*******************************************************************************
* File Name: cycfg_peripherals.h
*
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_PERIPHERALS_H)
#define CYCFG_PERIPHERALS_H
// #include "cycfg_notices.h"
#include "cy_scb_uart.h"
#include "cy_sysclk.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#if defined(__cplusplus)
extern "C" {
#endif
#define CYBSP_UART_ENABLED 1U
#define CYBSP_UART_HW SCB5
#define CYBSP_UART_IRQ scb_5_interrupt_IRQn
extern const cy_stc_scb_uart_config_t CYBSP_UART_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_UART_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_PERIPHERALS_H */

89
bootloader/mcuboot/boot/cypress/platforms/cycfg_pins.c Normal file
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/*******************************************************************************
* File Name: cycfg_pins.c
*
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_pins.h"
const cy_stc_gpio_pin_config_t CYBSP_UART_RX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
.hsiom = CYBSP_UART_RX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_UART_RX_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_UART_RX_PORT_NUM,
.channel_num = CYBSP_UART_RX_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_UART_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_UART_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_UART_TX_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_UART_TX_PORT_NUM,
.channel_num = CYBSP_UART_TX_PIN,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_pins(void)
{
Cy_GPIO_Pin_Init(CYBSP_UART_RX_PORT, CYBSP_UART_RX_PIN, &CYBSP_UART_RX_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_UART_RX_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_UART_TX_PORT, CYBSP_UART_TX_PIN, &CYBSP_UART_TX_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_UART_TX_obj);
#endif //defined (CY_USING_HAL)
}

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/*******************************************************************************
* File Name: cycfg_pins.h
*
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_PINS_H)
#define CYCFG_PINS_H
#include "cy_gpio.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cycfg_routing.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define CYBSP_UART_RX_ENABLED 1U
#define CYBSP_UART_RX_PORT GPIO_PRT5
#define CYBSP_UART_RX_PORT_NUM 5U
#define CYBSP_UART_RX_PIN 0U
#define CYBSP_UART_RX_NUM 0U
#define CYBSP_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_UART_RX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_5_pin_0_HSIOM
#define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
#define CYBSP_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_UART_RX_HAL_PORT_PIN P5_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
#endif //defined (CY_USING_HAL)
#define CYBSP_UART_TX_ENABLED 1U
#define CYBSP_UART_TX_PORT GPIO_PRT5
#define CYBSP_UART_TX_PORT_NUM 5U
#define CYBSP_UART_TX_PIN 1U
#define CYBSP_UART_TX_NUM 1U
#define CYBSP_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_UART_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_5_pin_1_HSIOM
#define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
#define CYBSP_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_UART_TX_HAL_PORT_PIN P5_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_UART_RX_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_UART_RX_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_UART_TX_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_UART_TX_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_pins(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_PINS_H */

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/*******************************************************************************
* File Name: cycfg_routing.c
*
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.4.0.1889
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_routing.h"
void init_cycfg_routing(void)
{
}

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/*******************************************************************************
* File Name: cycfg_routing.h
*
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.4.0.1889
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_ROUTING_H)
#define CYCFG_ROUTING_H
#if defined(__cplusplus)
extern "C" {
#endif
void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_ROUTING_H */

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/*******************************************************************************
* File Name: cycfg_system.c
*
* Description:
* System configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_system.h"
#define CY_CFG_SYSCLK_ECO_ERROR 1
#define CY_CFG_SYSCLK_ALTHF_ERROR 2
#define CY_CFG_SYSCLK_PLL_ERROR 3
#define CY_CFG_SYSCLK_FLL_ERROR 4
#define CY_CFG_SYSCLK_WCO_ERROR 5
#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
#define CY_CFG_SYSCLK_FLL_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_ILO_ENABLED 1
#define CY_CFG_SYSCLK_IMO_ENABLED 1
#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
#define CY_CFG_SYSCLK_PLL0_ENABLED 1
#define CY_CFG_SYSCLK_PLL1_ENABLED 1
#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
#define CY_CFG_SYSCLK_WCO_ENABLED 1
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
{
.fllMult = 500U,
.refDiv = 20U,
.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
.enableOutputDiv = true,
.lockTolerance = 10U,
.igain = 9U,
.pgain = 5U,
.settlingCount = 8U,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
.cco_Freq = 355U,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 1U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 2U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
{
.feedbackDiv = 36,
.referenceDiv = 1,
.outputDiv = 2,
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
};
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig =
{
.feedbackDiv = 30,
.referenceDiv = 1,
.outputDiv = 5,
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
};
__WEAK void cycfg_ClockStartupError(uint32_t error)
{
(void)error; /* Suppress the compiler warning */
while(1);
}
__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
{
Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);
}
__STATIC_INLINE void Cy_SysClk_ClkBakInit()
{
Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
}
__STATIC_INLINE void Cy_SysClk_ClkFastInit()
{
Cy_SysClk_ClkFastSetDivider(0U);
}
__STATIC_INLINE void Cy_SysClk_FllInit()
{
if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
}
}
__STATIC_INLINE void Cy_SysClk_ClkHf0Init()
{
Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
}
__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
}
__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
}
__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
}
__STATIC_INLINE void Cy_SysClk_IloInit()
{
/* The WDT is unlocked in the default startup code */
Cy_SysClk_IloEnable();
Cy_SysClk_IloHibernateOn(true);
}
__STATIC_INLINE void Cy_SysClk_ClkLfInit()
{
/* The WDT is unlocked in the default startup code */
Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
}
__STATIC_INLINE void Cy_SysClk_ClkPath0Init()
{
Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPath1Init()
{
Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPath2Init()
{
Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
{
Cy_SysClk_ClkPeriSetDivider(1U);
}
__STATIC_INLINE void Cy_SysClk_Pll0Init()
{
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
}
__STATIC_INLINE void Cy_SysClk_Pll1Init()
{
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
}
__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
{
Cy_SysClk_ClkSlowSetDivider(0U);
}
__STATIC_INLINE void Cy_SysClk_ClkTimerInit()
{
Cy_SysClk_ClkTimerDisable();
Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
Cy_SysClk_ClkTimerSetDivider(0U);
Cy_SysClk_ClkTimerEnable();
}
__STATIC_INLINE void Cy_SysClk_WcoInit()
{
(void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
(void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
}
}
void init_cycfg_system(void)
{
/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
Cy_SysLib_SetWaitStates(false, 150UL);
#ifdef CY_CFG_PWR_ENABLED
#ifdef CY_CFG_PWR_INIT
init_cycfg_power();
#else
#warning Power system will not be configured. Update power personality to v1.20 or later.
#endif /* CY_CFG_PWR_INIT */
#endif /* CY_CFG_PWR_ENABLED */
/* Reset the core clock path to default and disable all the FLLs/PLLs */
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkFastSetDivider(0U);
Cy_SysClk_ClkPeriSetDivider(1U);
Cy_SysClk_ClkSlowSetDivider(0U);
for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
{
(void)Cy_SysClk_PllDisable(pll);
}
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
(CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
{
Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
}
Cy_SysClk_FllDisable();
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
#ifdef CY_IP_MXBLESS
(void)Cy_BLE_EcoReset();
#endif
/* Enable all source clocks */
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
Cy_SysClk_PiloInit();
#endif
#ifdef CY_CFG_SYSCLK_WCO_ENABLED
Cy_SysClk_WcoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
Cy_SysClk_ClkLfInit();
#endif
#ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
Cy_SysClk_AltHfInit();
#endif
#ifdef CY_CFG_SYSCLK_ECO_ENABLED
Cy_SysClk_EcoInit();
#endif
#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
Cy_SysClk_ExtClkInit();
#endif
/* Configure CPU clock dividers */
#ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
Cy_SysClk_ClkFastInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
Cy_SysClk_ClkPeriInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
Cy_SysClk_ClkSlowInit();
#endif
#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
/* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
#else
#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
Cy_SysClk_ClkPath1Init();
#endif
#endif
/* Configure Path Clocks */
#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
Cy_SysClk_ClkPath0Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
Cy_SysClk_ClkPath2Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
Cy_SysClk_ClkPath3Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
Cy_SysClk_ClkPath4Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
Cy_SysClk_ClkPath5Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
Cy_SysClk_ClkPath6Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
Cy_SysClk_ClkPath7Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
Cy_SysClk_ClkPath8Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
Cy_SysClk_ClkPath9Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
Cy_SysClk_ClkPath10Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
Cy_SysClk_ClkPath11Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
Cy_SysClk_ClkPath12Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
Cy_SysClk_ClkPath13Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
Cy_SysClk_ClkPath14Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
Cy_SysClk_ClkPath15Init();
#endif
/* Configure and enable FLL */
#ifdef CY_CFG_SYSCLK_FLL_ENABLED
Cy_SysClk_FllInit();
#endif
Cy_SysClk_ClkHf0Init();
#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
/* Apply the ClkPath1 user setting */
Cy_SysClk_ClkPath1Init();
#endif
#endif
/* Configure and enable PLLs */
#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
Cy_SysClk_Pll0Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL1_ENABLED
Cy_SysClk_Pll1Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL2_ENABLED
Cy_SysClk_Pll2Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL3_ENABLED
Cy_SysClk_Pll3Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL4_ENABLED
Cy_SysClk_Pll4Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL5_ENABLED
Cy_SysClk_Pll5Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL6_ENABLED
Cy_SysClk_Pll6Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL7_ENABLED
Cy_SysClk_Pll7Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL8_ENABLED
Cy_SysClk_Pll8Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL9_ENABLED
Cy_SysClk_Pll9Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL10_ENABLED
Cy_SysClk_Pll10Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL11_ENABLED
Cy_SysClk_Pll11Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL12_ENABLED
Cy_SysClk_Pll12Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL13_ENABLED
Cy_SysClk_Pll13Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL14_ENABLED
Cy_SysClk_Pll14Init();
#endif
/* Configure HF clocks */
#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
Cy_SysClk_ClkHf1Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
Cy_SysClk_ClkHf2Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
Cy_SysClk_ClkHf3Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
Cy_SysClk_ClkHf4Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
Cy_SysClk_ClkHf5Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
Cy_SysClk_ClkHf6Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
Cy_SysClk_ClkHf7Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
Cy_SysClk_ClkHf8Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
Cy_SysClk_ClkHf9Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
Cy_SysClk_ClkHf10Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
Cy_SysClk_ClkHf11Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
Cy_SysClk_ClkHf12Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
Cy_SysClk_ClkHf13Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
Cy_SysClk_ClkHf14Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
Cy_SysClk_ClkHf15Init();
#endif
/* Configure miscellaneous clocks */
#ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
Cy_SysClk_ClkTimerInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
Cy_SysClk_ClkAltSysTickInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
Cy_SysClk_ClkPumpInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
Cy_SysClk_ClkBakInit();
#endif
/* Configure default enabled clocks */
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
Cy_SysClk_IloInit();
#else
Cy_SysClk_IloDisable();
#endif
#ifndef CY_CFG_SYSCLK_IMO_ENABLED
#error the IMO must be enabled for proper chip operation
#endif
#ifdef CY_CFG_SYSCLK_MFO_ENABLED
Cy_SysClk_MfoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
Cy_SysClk_ClkMfInit();
#endif
/* Set accurate flash wait states */
#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
#endif
/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
SystemCoreClockUpdate();
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
#endif //defined (CY_USING_HAL)
}

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/*******************************************************************************
* File Name: cycfg_system.h
*
* Description:
* System configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_SYSTEM_H)
#define CYCFG_SYSTEM_H
#include "cy_sysclk.h"
#include "cy_systick.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cy_gpio.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define cpuss_0_dap_0_ENABLED 1U
#define srss_0_clock_0_ENABLED 1U
#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
#define srss_0_clock_0_bakclk_0_ENABLED 1U
#define srss_0_clock_0_fastclk_0_ENABLED 1U
#define srss_0_clock_0_fll_0_ENABLED 1U
#define srss_0_clock_0_hfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF0 0UL
#define srss_0_clock_0_hfclk_2_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF2 2UL
#define srss_0_clock_0_hfclk_3_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF3 3UL
#define srss_0_clock_0_hfclk_4_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF4 4UL
#define srss_0_clock_0_ilo_0_ENABLED 1U
#define srss_0_clock_0_imo_0_ENABLED 1U
#define srss_0_clock_0_lfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
#define srss_0_clock_0_pathmux_0_ENABLED 1U
#define srss_0_clock_0_pathmux_1_ENABLED 1U
#define srss_0_clock_0_pathmux_2_ENABLED 1U
#define srss_0_clock_0_periclk_0_ENABLED 1U
#define srss_0_clock_0_pll_0_ENABLED 1U
#define srss_0_clock_0_pll_1_ENABLED 1U
#define srss_0_clock_0_slowclk_0_ENABLED 1U
#define srss_0_clock_0_timerclk_0_ENABLED 1U
#define srss_0_clock_0_wco_0_ENABLED 1U
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_system(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_SYSTEM_H */

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/***************************************************************************//**
* \file cy_retarget_io.c
*
* \brief
* Provides APIs for retargeting stdio to UART hardware contained on the Cypress
* kits.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cy_retarget_io_pdl.h"
#include "cycfg_peripherals.h"
#include "cy_sysint.h"
#include "cy_scb_uart.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* Tracks the previous character sent to output stream */
#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
static char cy_retarget_io_stdout_prev_char = 0;
#endif /* CY_RETARGET_IO_CONVERT_LF_TO_CRLF */
cy_stc_scb_uart_context_t CYBSP_UART_context;
static uint8_t cy_retarget_io_getchar(void);
static void cy_retarget_io_putchar(char c);
#if defined(__ARMCC_VERSION) /* ARM-MDK */
/***************************************************************************
* Function Name: fputc
***************************************************************************/
__attribute__((weak)) int fputc(int ch, FILE *f)
{
(void)f;
#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
if ((char)ch == '\n' && cy_retarget_io_stdout_prev_char != '\r')
{
cy_retarget_io_putchar('\r');
}
cy_retarget_io_stdout_prev_char = (char)ch;
#endif /* CY_RETARGET_IO_CONVERT_LF_TO_CRLF */
cy_retarget_io_putchar(ch);
return (ch);
}
#elif defined (__ICCARM__) /* IAR */
#include <yfuns.h>
/***************************************************************************
* Function Name: __write
***************************************************************************/
__weak size_t __write(int handle, const unsigned char * buffer, size_t size)
{
size_t nChars = 0;
/* This template only writes to "standard out", for all other file
* handles it returns failure. */
if (handle != _LLIO_STDOUT)
{
return (_LLIO_ERROR);
}
if (buffer != NULL)
{
for (/* Empty */; nChars < size; ++nChars)
{
#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
if (*buffer == '\n' && cy_retarget_io_stdout_prev_char != '\r')
{
cy_retarget_io_putchar('\r');
}
cy_retarget_io_stdout_prev_char = *buffer;
#endif /* CY_RETARGET_IO_CONVERT_LF_TO_CRLF */
cy_retarget_io_putchar(*buffer);
++buffer;
}
}
return (nChars);
}
#else /* (__GNUC__) GCC */
/* Add an explicit reference to the floating point printf library to allow
the usage of floating point conversion specifier. */
__asm (".global _printf_float");
/***************************************************************************
* Function Name: _write
***************************************************************************/
__attribute__((weak)) int _write (int fd, const char *ptr, int len)
{
int nChars = 0;
(void)fd;
if (ptr != NULL)
{
for (/* Empty */; nChars < len; ++nChars)
{
#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
if (*ptr == '\n' && cy_retarget_io_stdout_prev_char != '\r')
{
cy_retarget_io_putchar('\r');
}
cy_retarget_io_stdout_prev_char = *ptr;
#endif /* CY_RETARGET_IO_CONVERT_LF_TO_CRLF */
cy_retarget_io_putchar((uint32_t)*ptr);
++ptr;
}
}
return (nChars);
}
#endif
#if defined(__ARMCC_VERSION) /* ARM-MDK */
/***************************************************************************
* Function Name: fgetc
***************************************************************************/
__attribute__((weak)) int fgetc(FILE *f)
{
(void)f;
return (cy_retarget_io_getchar());
}
#elif defined (__ICCARM__) /* IAR */
__weak size_t __read(int handle, unsigned char * buffer, size_t size)
{
/* This template only reads from "standard in", for all other file
handles it returns failure. */
if ((handle != _LLIO_STDIN) || (buffer == NULL))
{
return (_LLIO_ERROR);
}
else
{
*buffer = cy_retarget_io_getchar();
return (1);
}
}
#else /* (__GNUC__) GCC */
/* Add an explicit reference to the floating point scanf library to allow
the usage of floating point conversion specifier. */
__asm (".global _scanf_float");
__attribute__((weak)) int _read (int fd, char *ptr, int len)
{
int nChars = 0;
(void)fd;
if (ptr != NULL)
{
for(/* Empty */;nChars < len;++ptr)
{
*ptr = (char)cy_retarget_io_getchar();
++nChars;
if((*ptr == '\n') || (*ptr == '\r'))
{
break;
}
}
}
return (nChars);
}
#endif
static uint8_t cy_retarget_io_getchar(void)
{
uint32_t read_value = Cy_SCB_UART_Get(CYBSP_UART_HW);
while (read_value == CY_SCB_UART_RX_NO_DATA)
{
read_value = Cy_SCB_UART_Get(CYBSP_UART_HW);
}
return (uint8_t)read_value;
}
static void cy_retarget_io_putchar(char c)
{
uint32_t count = 0;
while (count == 0)
{
count = Cy_SCB_UART_Put(CYBSP_UART_HW, c);
}
}
static cy_rslt_t cy_retarget_io_pdl_setbaud(CySCB_Type *base, uint32_t baudrate)
{
cy_rslt_t result = CY_RSLT_TYPE_ERROR;
uint8_t oversample_value = 8u;
uint8_t frac_bits = 0u;
uint32_t divider;
Cy_SCB_UART_Disable(base, NULL);
result = (cy_rslt_t) Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0);
divider = ((Cy_SysClk_ClkPeriGetFrequency() * (1 << frac_bits)) + ((baudrate * oversample_value) / 2)) / (baudrate * oversample_value) - 1;
if (result == CY_RSLT_SUCCESS)
{
result = (cy_rslt_t) Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0u, divider);
}
if (result == CY_RSLT_SUCCESS)
{
result = Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0u);
}
Cy_SCB_UART_Enable(base);
return result;
}
cy_rslt_t cy_retarget_io_pdl_init(uint32_t baudrate)
{
cy_rslt_t result = CY_RSLT_TYPE_ERROR;
result = (cy_rslt_t)Cy_SCB_UART_Init(CYBSP_UART_HW, &CYBSP_UART_config, &CYBSP_UART_context);
if (result == CY_RSLT_SUCCESS)
{
result = cy_retarget_io_pdl_setbaud(CYBSP_UART_HW, baudrate);
}
if (result == CY_RSLT_SUCCESS)
{
Cy_SCB_UART_Enable(CYBSP_UART_HW);
}
return result;
}
/**
* @brief Wait while UART completes transfer. Try for tries_count times -
* once each 10 millisecons.
*/
void cy_retarget_io_wait_tx_complete(CySCB_Type *base, uint32_t tries_count)
{
while(tries_count > 0)
{
if (!Cy_SCB_UART_IsTxComplete(base)) {
Cy_SysLib_DelayCycles(10 * cy_delayFreqKhz);
tries_count -= 1;
} else {
return;
}
}
}
void cy_retarget_io_pdl_deinit()
{
Cy_SCB_UART_DeInit(CYBSP_UART_HW);
}
#if defined(__cplusplus)
}
#endif

62
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/***************************************************************************//**
* \file cy_retarget_io.h
*
* \brief
* Provides APIs for transmitting messages to or from the board via standard
* printf/scanf functions. Messages are transmitted over a UART connection which
* is generally connected to a host machine. Transmission is done at 115200 baud
* using the tx and rx pins provided by the user of this library. The UART
* instance is made available via cy_retarget_io_uart_obj in case any changes
* to the default configuration are desired.
* NOTE: If the application is built using newlib-nano, by default, floating
* point format strings (%f) are not supported. To enable this support you must
* add '-u _printf_float' to the linker command line.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#pragma once
#include <stdio.h>
#include "cy_result.h"
#include "cy_pdl.h"
#if defined(__cplusplus)
extern "C" {
#endif
/** UART baud rate */
#define CY_RETARGET_IO_BAUDRATE (115200)
/** Defining this macro enables conversion of line feed (LF) into carriage
* return followed by line feed (CR & LF) on the output direction (STDOUT). You
* can define this macro through the DEFINES variable in the application
* Makefile.
*/
#define CY_RETARGET_IO_CONVERT_LF_TO_CRLF
cy_rslt_t cy_retarget_io_pdl_init(uint32_t baudrate);
void cy_retarget_io_wait_tx_complete(CySCB_Type *base, uint32_t tries_count);
void cy_retarget_io_pdl_deinit(void);
#if defined(__cplusplus)
}
#endif

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################################################################################
# \file toolchains.mk
# \version 1.0
#
# \brief
# Makefile to describe supported toolchains for Cypress MCUBoot based applications.
#
################################################################################
# \copyright
# Copyright 2018-2019 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
################################################################################
include common_libs.mk
# Compilers
GCC_ARM := 1
IAR := 2
ARM := 3
OTHER := 4
ifeq ($(MAKEINFO), 1)
$(info $(COMPILER))
endif
# Detect host OS to make resolving compiler pathes easier
UNAME_S := $(shell uname -s)
ifeq ($(UNAME_S), Darwin)
HOST_OS = osx
else
ifeq ($(UNAME_S), Linux)
HOST_OS = linux
else
HOST_OS = win
endif
endif
# Path to the compiler installation
# NOTE: Absolute pathes for now for the sake of development
ifeq ($(HOST_OS), win)
ifeq ($(COMPILER), GCC_ARM)
TOOLCHAIN_PATH ?= c:/Users/$(USERNAME)/ModusToolbox/tools_2.2/gcc
MY_TOOLCHAIN_PATH:=$(subst \,/,$(TOOLCHAIN_PATH))
TOOLCHAIN_PATH := $(MY_TOOLCHAIN_PATH)
GCC_PATH := $(TOOLCHAIN_PATH)
# executables
CC := "$(GCC_PATH)/bin/arm-none-eabi-gcc"
LD := $(CC)
endif
else ifeq ($(HOST_OS), osx)
TOOLCHAIN_PATH ?= /opt/gcc-arm-none-eabi
GCC_PATH := $(TOOLCHAIN_PATH)
CC := "$(GCC_PATH)/bin/arm-none-eabi-gcc"
LD := $(CC)
else ifeq ($(HOST_OS), linux)
TOOLCHAIN_PATH ?= /opt/gcc-arm-none-eabi
GCC_PATH := $(TOOLCHAIN_PATH)
# executables
CC := "$(GCC_PATH)/bin/arm-none-eabi-gcc"
LD := $(CC)
endif
PDL_ELFTOOL := "hal/tools/$(HOST_OS)/elf/cymcuelftool"
OBJDUMP := "$(GCC_PATH)/bin/arm-none-eabi-objdump"
OBJCOPY := "$(GCC_PATH)/bin/arm-none-eabi-objcopy"
# Set flags for toolchain executables
ifeq ($(COMPILER), GCC_ARM)
# set build-in compiler flags
CFLAGS_COMMON := -mcpu=cortex-$(CORE_SIFFX) -mthumb -mfloat-abi=soft -fno-stack-protector -ffunction-sections -fdata-sections -ffat-lto-objects -fstrict-aliasing -g -Wall -Wextra
ifeq ($(BUILDCFG), Debug)
CFLAGS_COMMON += -Og -g3
else ifeq ($(BUILDCFG), Release)
CFLAGS_COMMON += -Os -g
else
$(error BUILDCFG : '$(BUILDCFG)' is not supported)
endif
# add defines and includes
CFLAGS := $(CFLAGS_COMMON) $(INCLUDES)
CC_DEPEND = -MD -MP -MF
LDFLAGS_COMMON := -mcpu=cortex-$(CORE_SIFFX) -mthumb -specs=nano.specs -ffunction-sections -fdata-sections -Wl,--gc-sections -L "$(GCC_PATH)/lib/gcc/arm-none-eabi/7.2.1/thumb/v6-m" -ffat-lto-objects -g --enable-objc-gc
ifeq ($(BUILDCFG), Debug)
LDFLAGS_COMMON += -Og
else ifeq ($(BUILDCFG), Release)
LDFLAGS_COMMON += -Os
else
$(error BUILDCFG : '$(BUILDCFG)' is not supported)
endif
LDFLAGS_NANO := -L "$(GCC_PATH)/arm-none-eabi/lib/thumb/v6-m"
LDFLAGS := $(LDFLAGS_COMMON) $(LDFLAGS_NANO)
endif