Initial commit
Initial commit.
This commit is contained in:
kntran1
537
bootloader/mcuboot/boot/cypress/platforms/cycfg_system.c
Normal file
537
bootloader/mcuboot/boot/cypress/platforms/cycfg_system.c
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@@ -0,0 +1,537 @@
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/*******************************************************************************
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* File Name: cycfg_system.c
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*
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* Description:
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* System configuration
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* This file was automatically generated and should not be modified.
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* Device Configurator: 2.0.0.1483
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* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#include "cycfg_system.h"
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#define CY_CFG_SYSCLK_ECO_ERROR 1
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#define CY_CFG_SYSCLK_ALTHF_ERROR 2
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#define CY_CFG_SYSCLK_PLL_ERROR 3
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#define CY_CFG_SYSCLK_FLL_ERROR 4
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#define CY_CFG_SYSCLK_WCO_ERROR 5
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#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
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#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
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#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
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#define CY_CFG_SYSCLK_FLL_ENABLED 1
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#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
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#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
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#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
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#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
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#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
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#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
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#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
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#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 100UL
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#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
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#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
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#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
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#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
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#define CY_CFG_SYSCLK_ILO_ENABLED 1
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#define CY_CFG_SYSCLK_IMO_ENABLED 1
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#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
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#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
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#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
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#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
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#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
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#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
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#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
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#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
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#define CY_CFG_SYSCLK_PLL0_ENABLED 1
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#define CY_CFG_SYSCLK_PLL1_ENABLED 1
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#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
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#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
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#define CY_CFG_SYSCLK_WCO_ENABLED 1
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static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
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{
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.fllMult = 500U,
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.refDiv = 20U,
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.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
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.enableOutputDiv = true,
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.lockTolerance = 10U,
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.igain = 9U,
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.pgain = 5U,
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.settlingCount = 8U,
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.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
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.cco_Freq = 355U,
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};
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
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{
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.type = CYHAL_RSC_CLKPATH,
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.block_num = 0U,
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.channel_num = 0U,
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};
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#endif //defined (CY_USING_HAL)
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
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{
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.type = CYHAL_RSC_CLKPATH,
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.block_num = 1U,
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.channel_num = 0U,
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};
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#endif //defined (CY_USING_HAL)
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
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{
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.type = CYHAL_RSC_CLKPATH,
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.block_num = 2U,
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.channel_num = 0U,
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};
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#endif //defined (CY_USING_HAL)
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static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
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{
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.feedbackDiv = 36,
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.referenceDiv = 1,
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.outputDiv = 2,
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.lfMode = false,
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.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
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};
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static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig =
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{
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.feedbackDiv = 30,
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.referenceDiv = 1,
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.outputDiv = 5,
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.lfMode = false,
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.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
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};
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__WEAK void cycfg_ClockStartupError(uint32_t error)
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{
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(void)error; /* Suppress the compiler warning */
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while(1);
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}
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__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
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{
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Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);
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}
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__STATIC_INLINE void Cy_SysClk_ClkBakInit()
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{
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Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
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}
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__STATIC_INLINE void Cy_SysClk_ClkFastInit()
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{
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Cy_SysClk_ClkFastSetDivider(0U);
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}
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__STATIC_INLINE void Cy_SysClk_FllInit()
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{
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if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
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{
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cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
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}
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if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
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{
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cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
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}
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}
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__STATIC_INLINE void Cy_SysClk_ClkHf0Init()
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{
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Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
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Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
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}
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__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
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{
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Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
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Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
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Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
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}
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__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
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{
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Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
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Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
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Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
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}
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__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
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{
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Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
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Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
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Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
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}
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__STATIC_INLINE void Cy_SysClk_IloInit()
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{
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/* The WDT is unlocked in the default startup code */
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Cy_SysClk_IloEnable();
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Cy_SysClk_IloHibernateOn(true);
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}
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__STATIC_INLINE void Cy_SysClk_ClkLfInit()
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{
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/* The WDT is unlocked in the default startup code */
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Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
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}
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__STATIC_INLINE void Cy_SysClk_ClkPath0Init()
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{
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Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
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}
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__STATIC_INLINE void Cy_SysClk_ClkPath1Init()
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{
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Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
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}
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__STATIC_INLINE void Cy_SysClk_ClkPath2Init()
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{
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Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
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}
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__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
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{
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Cy_SysClk_ClkPeriSetDivider(1U);
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}
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__STATIC_INLINE void Cy_SysClk_Pll0Init()
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{
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if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
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{
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cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
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}
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if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
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{
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cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
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}
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}
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__STATIC_INLINE void Cy_SysClk_Pll1Init()
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{
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if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig))
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{
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cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
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}
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if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u))
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{
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cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
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}
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}
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__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
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{
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Cy_SysClk_ClkSlowSetDivider(0U);
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}
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__STATIC_INLINE void Cy_SysClk_ClkTimerInit()
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{
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Cy_SysClk_ClkTimerDisable();
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Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
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Cy_SysClk_ClkTimerSetDivider(0U);
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Cy_SysClk_ClkTimerEnable();
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}
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__STATIC_INLINE void Cy_SysClk_WcoInit()
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{
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(void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
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(void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
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if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
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{
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cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
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}
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}
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void init_cycfg_system(void)
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{
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/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
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Cy_SysLib_SetWaitStates(false, 150UL);
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#ifdef CY_CFG_PWR_ENABLED
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#ifdef CY_CFG_PWR_INIT
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init_cycfg_power();
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#else
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#warning Power system will not be configured. Update power personality to v1.20 or later.
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#endif /* CY_CFG_PWR_INIT */
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#endif /* CY_CFG_PWR_ENABLED */
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/* Reset the core clock path to default and disable all the FLLs/PLLs */
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Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
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Cy_SysClk_ClkFastSetDivider(0U);
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Cy_SysClk_ClkPeriSetDivider(1U);
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Cy_SysClk_ClkSlowSetDivider(0U);
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for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
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{
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(void)Cy_SysClk_PllDisable(pll);
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}
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Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
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if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
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(CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
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{
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Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
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}
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Cy_SysClk_FllDisable();
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Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
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Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
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#ifdef CY_IP_MXBLESS
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(void)Cy_BLE_EcoReset();
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#endif
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/* Enable all source clocks */
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#ifdef CY_CFG_SYSCLK_PILO_ENABLED
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Cy_SysClk_PiloInit();
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#endif
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#ifdef CY_CFG_SYSCLK_WCO_ENABLED
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Cy_SysClk_WcoInit();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
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Cy_SysClk_ClkLfInit();
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#endif
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#ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
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Cy_SysClk_AltHfInit();
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#endif
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#ifdef CY_CFG_SYSCLK_ECO_ENABLED
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Cy_SysClk_EcoInit();
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#endif
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#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
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Cy_SysClk_ExtClkInit();
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#endif
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/* Configure CPU clock dividers */
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#ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
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Cy_SysClk_ClkFastInit();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
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Cy_SysClk_ClkPeriInit();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
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Cy_SysClk_ClkSlowInit();
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#endif
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#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
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/* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
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Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
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Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
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#else
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#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
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Cy_SysClk_ClkPath1Init();
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#endif
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#endif
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/* Configure Path Clocks */
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#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
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Cy_SysClk_ClkPath0Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
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Cy_SysClk_ClkPath2Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
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Cy_SysClk_ClkPath3Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
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Cy_SysClk_ClkPath4Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
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Cy_SysClk_ClkPath5Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
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Cy_SysClk_ClkPath6Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
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Cy_SysClk_ClkPath7Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
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Cy_SysClk_ClkPath8Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
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Cy_SysClk_ClkPath9Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
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Cy_SysClk_ClkPath10Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
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Cy_SysClk_ClkPath11Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
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Cy_SysClk_ClkPath12Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
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Cy_SysClk_ClkPath13Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
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Cy_SysClk_ClkPath14Init();
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#endif
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#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
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Cy_SysClk_ClkPath15Init();
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#endif
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/* Configure and enable FLL */
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#ifdef CY_CFG_SYSCLK_FLL_ENABLED
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Cy_SysClk_FllInit();
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#endif
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Cy_SysClk_ClkHf0Init();
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#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
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||||
#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
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/* Apply the ClkPath1 user setting */
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||||
Cy_SysClk_ClkPath1Init();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Configure and enable PLLs */
|
||||
#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
|
||||
Cy_SysClk_Pll0Init();
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||||
#endif
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||||
#ifdef CY_CFG_SYSCLK_PLL1_ENABLED
|
||||
Cy_SysClk_Pll1Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL2_ENABLED
|
||||
Cy_SysClk_Pll2Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL3_ENABLED
|
||||
Cy_SysClk_Pll3Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL4_ENABLED
|
||||
Cy_SysClk_Pll4Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL5_ENABLED
|
||||
Cy_SysClk_Pll5Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL6_ENABLED
|
||||
Cy_SysClk_Pll6Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL7_ENABLED
|
||||
Cy_SysClk_Pll7Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL8_ENABLED
|
||||
Cy_SysClk_Pll8Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL9_ENABLED
|
||||
Cy_SysClk_Pll9Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL10_ENABLED
|
||||
Cy_SysClk_Pll10Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL11_ENABLED
|
||||
Cy_SysClk_Pll11Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL12_ENABLED
|
||||
Cy_SysClk_Pll12Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL13_ENABLED
|
||||
Cy_SysClk_Pll13Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL14_ENABLED
|
||||
Cy_SysClk_Pll14Init();
|
||||
#endif
|
||||
|
||||
/* Configure HF clocks */
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
|
||||
Cy_SysClk_ClkHf1Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
|
||||
Cy_SysClk_ClkHf2Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
|
||||
Cy_SysClk_ClkHf3Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
|
||||
Cy_SysClk_ClkHf4Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
|
||||
Cy_SysClk_ClkHf5Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
|
||||
Cy_SysClk_ClkHf6Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
|
||||
Cy_SysClk_ClkHf7Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
|
||||
Cy_SysClk_ClkHf8Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
|
||||
Cy_SysClk_ClkHf9Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
|
||||
Cy_SysClk_ClkHf10Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
|
||||
Cy_SysClk_ClkHf11Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
|
||||
Cy_SysClk_ClkHf12Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
|
||||
Cy_SysClk_ClkHf13Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
|
||||
Cy_SysClk_ClkHf14Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
|
||||
Cy_SysClk_ClkHf15Init();
|
||||
#endif
|
||||
|
||||
/* Configure miscellaneous clocks */
|
||||
#ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
|
||||
Cy_SysClk_ClkTimerInit();
|
||||
#endif
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
|
||||
Cy_SysClk_ClkAltSysTickInit();
|
||||
#endif
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
|
||||
Cy_SysClk_ClkPumpInit();
|
||||
#endif
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
|
||||
Cy_SysClk_ClkBakInit();
|
||||
#endif
|
||||
|
||||
/* Configure default enabled clocks */
|
||||
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
|
||||
Cy_SysClk_IloInit();
|
||||
#else
|
||||
Cy_SysClk_IloDisable();
|
||||
#endif
|
||||
|
||||
#ifndef CY_CFG_SYSCLK_IMO_ENABLED
|
||||
#error the IMO must be enabled for proper chip operation
|
||||
#endif
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_MFO_ENABLED
|
||||
Cy_SysClk_MfoInit();
|
||||
#endif
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
|
||||
Cy_SysClk_ClkMfInit();
|
||||
#endif
|
||||
|
||||
/* Set accurate flash wait states */
|
||||
#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
|
||||
Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
|
||||
#endif
|
||||
|
||||
/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
Reference in New Issue
Block a user