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Initial commit.
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kntran1
2026-03-23 14:40:39 -05:00
parent e84b2b4166
commit 4e2a5258a5
872 changed files with 165227 additions and 0 deletions
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34
bootloader/mcuboot/boot/espressif/port/esp32/bootloader-multi.conf Normal file
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# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
#
# SPDX-License-Identifier: Apache-2.0
CONFIG_ESP_FLASH_SIZE=4MB
CONFIG_ESP_BOOTLOADER_SIZE=0xF000
CONFIG_ESP_BOOTLOADER_OFFSET=0x1000
# Example of values to be used when multi image is enabled
# Notice that the OS layer and update agent must be aware
# of these regions
CONFIG_ESP_APPLICATION_SIZE=0x80000
CONFIG_ESP_IMAGE0_PRIMARY_START_ADDRESS=0x10000
CONFIG_ESP_IMAGE0_SECONDARY_START_ADDRESS=0x90000
CONFIG_ESP_IMAGE1_PRIMARY_START_ADDRESS=0x110000
CONFIG_ESP_IMAGE1_SECONDARY_START_ADDRESS=0x190000
CONFIG_ESP_SCRATCH_OFFSET=0x210000
CONFIG_ESP_SCRATCH_SIZE=0x40000
CONFIG_ESP_MCUBOOT_WDT_ENABLE=y
CONFIG_ESP_CONSOLE_UART=y
CONFIG_ESP_CONSOLE_UART_NUM=0
# Configures alternative UART port for console printing
# CONFIG_ESP_CONSOLE_UART_CUSTOM=y
# CONFIG_ESP_CONSOLE_UART_TX_GPIO=26
# CONFIG_ESP_CONSOLE_UART_RX_GPIO=25
# Enables multi image, if it is not defined, it is assumed
# only one updatable image
# CONFIG_ESP_IMAGE_NUMBER=2
# Enables multi image boot on independent processors
# (main host OS is not responsible for booting the second image)
# Use only with CONFIG_ESP_IMAGE_NUMBER=2
# CONFIG_ESP_MULTI_PROCESSOR_BOOT=y

101
bootloader/mcuboot/boot/espressif/port/esp32/bootloader.conf Normal file
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# SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
#
# SPDX-License-Identifier: Apache-2.0
CONFIG_ESP_FLASH_SIZE=4MB
CONFIG_ESP_BOOTLOADER_SIZE=0xF000
CONFIG_ESP_BOOTLOADER_OFFSET=0x1000
CONFIG_ESP_IMAGE0_PRIMARY_START_ADDRESS=0x10000
CONFIG_ESP_APPLICATION_SIZE=0x100000
CONFIG_ESP_IMAGE0_SECONDARY_START_ADDRESS=0x110000
CONFIG_ESP_MCUBOOT_WDT_ENABLE=y
CONFIG_ESP_SCRATCH_OFFSET=0x210000
CONFIG_ESP_SCRATCH_SIZE=0x40000
# When enabled, prevents updating image to an older version
# CONFIG_ESP_DOWNGRADE_PREVENTION=y
# This option makes downgrade prevention rely also on security
# counter (defined using imgtool) instead of only image version
# CONFIG_ESP_DOWNGRADE_PREVENTION_SECURITY_COUNTER=y
# Enables the MCUboot Serial Recovery, that allows the use of
# MCUMGR to upload a firmware through the serial port
# CONFIG_ESP_MCUBOOT_SERIAL=y
# Use sector erasing instead of entire image size erasing
# when uploading through Serial Recovery
# CONFIG_ESP_MCUBOOT_ERASE_PROGRESSIVELY=y
# GPIO used to boot on Serial Recovery
# CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT=32
# GPIO input type (0 for Pull-down, 1 for Pull-up)
# CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE=0
# GPIO signal value
# CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL=1
# Delay time for identify the GPIO signal
# CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S=5
# UART port used for serial communication
# CONFIG_ESP_SERIAL_BOOT_UART_NUM=1
# GPIO for Serial RX signal
# CONFIG_ESP_SERIAL_BOOT_GPIO_RX=25
# GPIO for Serial TX signal
# CONFIG_ESP_SERIAL_BOOT_GPIO_TX=26
CONFIG_ESP_CONSOLE_UART=y
CONFIG_ESP_CONSOLE_UART_NUM=0
# Configures alternative UART port for console printing
# CONFIG_ESP_CONSOLE_UART_CUSTOM=y
# CONFIG_ESP_CONSOLE_UART_TX_GPIO=26
# CONFIG_ESP_CONSOLE_UART_RX_GPIO=25
# Enables multi image, if it is not defined, it is assumed
# only one updatable image
# CONFIG_ESP_IMAGE_NUMBER=2
# Enables multi image boot on independent processors
# (main host OS is not responsible for booting the second image)
# Use only with CONFIG_ESP_IMAGE_NUMBER=2
# CONFIG_ESP_MULTI_PROCESSOR_BOOT=y
# Example of values to be used when multi image is enabled
# Notice that the OS layer and update agent must be aware
# of these regions
# CONFIG_ESP_APPLICATION_SIZE=0x80000
# CONFIG_ESP_IMAGE0_PRIMARY_START_ADDRESS=0x10000
# CONFIG_ESP_IMAGE0_SECONDARY_START_ADDRESS=0x90000
# CONFIG_ESP_IMAGE1_PRIMARY_START_ADDRESS=0x110000
# CONFIG_ESP_IMAGE1_SECONDARY_START_ADDRESS=0x190000
# CONFIG_ESP_SCRATCH_OFFSET=0x210000
# CONFIG_ESP_SCRATCH_SIZE=0x40000
# CONFIG_ESP_SIGN_EC256=y
# CONFIG_ESP_SIGN_ED25519=n
# CONFIG_ESP_SIGN_RSA=n
# CONFIG_ESP_SIGN_RSA_LEN=2048
# Use Tinycrypt lib for EC256 or ED25519 signing
# CONFIG_ESP_USE_TINYCRYPT=y
# Use Mbed TLS lib for RSA image signing
# CONFIG_ESP_USE_MBEDTLS=n
# It is strongly recommended to generate a new signing key
# using imgtool instead of use the existent sample
# CONFIG_ESP_SIGN_KEY_FILE=root-ec-p256.pem
# Hardware Secure Boot related options
# CONFIG_SECURE_SIGNED_ON_BOOT=1
# CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME=1
# CONFIG_SECURE_BOOT=1
# CONFIG_SECURE_BOOT_V2_ENABLED=1
# CONFIG_SECURE_BOOT_SUPPORTS_RSA=1
# Hardware Flash Encryption related options
# CONFIG_SECURE_FLASH_ENC_ENABLED=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE=1
# CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT=1
# CONFIG_SECURE_BOOT_ALLOW_JTAG=1
# CONFIG_SECURE_BOOT_ALLOW_ROM_BASIC=1
# Options for enabling eFuse emulation in Flash
# CONFIG_EFUSE_VIRTUAL=1
# CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH=1

144
bootloader/mcuboot/boot/espressif/port/esp32/ld/bootloader.ld Normal file
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/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Simplified memory map for the bootloader.
*
* The main purpose is to make sure the bootloader can load into main memory
* without overwriting itself.
*/
MEMORY
{
#ifdef CONFIG_ESP_MULTI_PROCESSOR_BOOT
iram_loader_seg (RWX) : org = 0x400AB900, len = 0x6500
#else
/* iram_loader_seg is currently placed on APP_CPU cache IRAM address range */
iram_loader_seg (RWX) : org = 0x40078000, len = 0x6500
#endif
iram_seg (RWX) : org = 0x40090000, len = 0x9000
dram_seg (RW) : org = 0x3FFF4700, len = 0xB900
}
/* Default entry point: */
ENTRY(main);
SECTIONS
{
.iram_loader.text :
{
. = ALIGN (16);
_loader_text_start = ABSOLUTE(.);
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
*libhal.a:*.*(.literal .text .literal.* .text.*)
*esp_mcuboot.*(.literal .text .literal.* .text.*)
*esp_loader.*(.literal .text .literal.* .text.*)
*main.*(.literal .text .literal.* .text.*)
*(.fini.literal)
*(.fini)
*(.gnu.version)
_loader_text_end = ABSOLUTE(.);
} > iram_loader_seg
.iram.text :
{
. = ALIGN (16);
*(.entry.text)
*(.init.literal)
*(.init)
} > iram_seg
.dram0.bss (NOLOAD) :
{
. = ALIGN (8);
_dram_start = ABSOLUTE(.);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
} >dram_seg
.dram0.data :
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
*(.jcr)
_data_end = ABSOLUTE(.);
} >dram_seg
.dram0.rodata :
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
*(.eh_frame)
. = (. + 3) & ~ 3;
/* C++ constructor and destructor tables, properly ordered: */
__init_array_start = ABSOLUTE(.);
KEEP (*crtbegin.*(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__init_array_end = ABSOLUTE(.);
KEEP (*crtbegin.*(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
_rodata_end = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
_dram_end = ABSOLUTE(.);
} >dram_seg
.iram.text :
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram .iram.*) /* catch stray IRAM_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} > iram_seg
}

179
bootloader/mcuboot/boot/espressif/port/esp32/serial_adapter.c Normal file
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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <bootutil/bootutil_log.h>
#include <esp_rom_uart.h>
#include <esp_rom_gpio.h>
#include <esp_rom_sys.h>
#include <soc/uart_periph.h>
#include <soc/gpio_struct.h>
#include <soc/io_mux_reg.h>
#include <soc/rtc.h>
#include <hal/gpio_types.h>
#include <hal/gpio_ll.h>
#include <hal/uart_ll.h>
#include <hal/clk_gate_ll.h>
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT
#define SERIAL_BOOT_GPIO_DETECT CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT
#else
#define SERIAL_BOOT_GPIO_DETECT GPIO_NUM_5
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL
#define SERIAL_BOOT_GPIO_DETECT_VAL CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL
#else
#define SERIAL_BOOT_GPIO_DETECT_VAL 1
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S
#define SERIAL_BOOT_DETECT_DELAY_S CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S
#else
#define SERIAL_BOOT_DETECT_DELAY_S 5
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE
#define SERIAL_BOOT_GPIO_INPUT_TYPE CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE
#else
// pull-down
#define SERIAL_BOOT_GPIO_INPUT_TYPE 0
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_UART_NUM
#define SERIAL_BOOT_UART_NUM CONFIG_ESP_SERIAL_BOOT_UART_NUM
#else
#define SERIAL_BOOT_UART_NUM ESP_ROM_UART_1
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_RX
#define SERIAL_BOOT_GPIO_RX CONFIG_ESP_SERIAL_BOOT_GPIO_RX
#else
#define SERIAL_BOOT_GPIO_RX GPIO_NUM_8
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_TX
#define SERIAL_BOOT_GPIO_TX CONFIG_ESP_SERIAL_BOOT_GPIO_TX
#else
#define SERIAL_BOOT_GPIO_TX GPIO_NUM_9
#endif
static uart_dev_t *serial_boot_uart_dev = (SERIAL_BOOT_UART_NUM == 0) ?
&UART0 :
&UART1;
void console_write(const char *str, int cnt)
{
uint32_t tx_len;
do {
tx_len = uart_ll_get_txfifo_len(serial_boot_uart_dev);
} while (tx_len < cnt);
uart_ll_write_txfifo(serial_boot_uart_dev, (const uint8_t *)str, cnt);
}
int console_read(char *str, int cnt, int *newline)
{
volatile uint32_t len = 0;
volatile uint32_t read_len = 0;
volatile bool stop = false;
do {
len = uart_ll_get_rxfifo_len(serial_boot_uart_dev);
if (len) {
for (uint32_t i = 0; i < len; i++) {
/* Read the character from the RX FIFO */
uart_ll_read_rxfifo(serial_boot_uart_dev, (uint8_t *)&str[read_len], 1);
read_len++;
if (read_len == cnt || str[read_len - 1] == '\n') {
stop = true;
break;
}
}
}
MCUBOOT_WATCHDOG_FEED();
esp_rom_delay_us(1000);
} while (!stop);
*newline = (str[read_len - 1] == '\n') ? 1 : 0;
return read_len;
}
int boot_console_init(void)
{
BOOT_LOG_INF("Initializing serial boot pins");
/* Enable GPIO for UART RX */
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_RX);
esp_rom_gpio_connect_in_signal(SERIAL_BOOT_GPIO_RX,
UART_PERIPH_SIGNAL(SERIAL_BOOT_UART_NUM, SOC_UART_RX_PIN_IDX),
0);
gpio_ll_input_enable(&GPIO, SERIAL_BOOT_GPIO_RX);
/* Enable GPIO for UART TX */
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_TX);
esp_rom_gpio_connect_out_signal(SERIAL_BOOT_GPIO_TX,
UART_PERIPH_SIGNAL(SERIAL_BOOT_UART_NUM, SOC_UART_TX_PIN_IDX),
0, 0);
gpio_ll_output_enable(&GPIO, SERIAL_BOOT_GPIO_TX);
uart_ll_set_sclk(serial_boot_uart_dev, UART_SCLK_APB);
uart_ll_set_mode_normal(serial_boot_uart_dev);
uart_ll_set_baudrate(serial_boot_uart_dev, 115200, UART_SCLK_APB);
uart_ll_set_stop_bits(serial_boot_uart_dev, 1u);
uart_ll_set_parity(serial_boot_uart_dev, UART_PARITY_DISABLE);
uart_ll_set_rx_tout(serial_boot_uart_dev, 16);
uart_ll_set_data_bit_num(serial_boot_uart_dev, UART_DATA_8_BITS);
uart_ll_set_tx_idle_num(serial_boot_uart_dev, 0);
uart_ll_set_hw_flow_ctrl(serial_boot_uart_dev, UART_HW_FLOWCTRL_DISABLE, 100);
periph_ll_enable_clk_clear_rst(PERIPH_UART0_MODULE + SERIAL_BOOT_UART_NUM);
uart_ll_txfifo_rst(serial_boot_uart_dev);
uart_ll_rxfifo_rst(serial_boot_uart_dev);
esp_rom_delay_us(50000);
return 0;
}
bool boot_serial_detect_pin(void)
{
bool detected = false;
int pin_value = 0;
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_DETECT);
gpio_ll_input_enable(&GPIO, SERIAL_BOOT_GPIO_DETECT);
switch (SERIAL_BOOT_GPIO_INPUT_TYPE) {
// Pull-down
case 0:
gpio_ll_pulldown_en(&GPIO, SERIAL_BOOT_GPIO_DETECT);
break;
// Pull-up
case 1:
gpio_ll_pullup_en(&GPIO, SERIAL_BOOT_GPIO_DETECT);
break;
}
esp_rom_delay_us(50000);
pin_value = gpio_ll_get_level(&GPIO, SERIAL_BOOT_GPIO_DETECT);
detected = (pin_value == SERIAL_BOOT_GPIO_DETECT_VAL);
esp_rom_delay_us(50000);
if (detected) {
if (SERIAL_BOOT_DETECT_DELAY_S > 0) {
/* The delay time is an approximation */
for (int i = 0; i < (SERIAL_BOOT_DETECT_DELAY_S * 100); i++) {
esp_rom_delay_us(10000);
pin_value = gpio_ll_get_level(&GPIO, SERIAL_BOOT_GPIO_DETECT);
detected = (pin_value == SERIAL_BOOT_GPIO_DETECT_VAL);
if (!detected) {
break;
}
}
}
}
return detected;
}

87
bootloader/mcuboot/boot/espressif/port/esp32c2/bootloader.conf Normal file
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# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
#
# SPDX-License-Identifier: Apache-2.0
CONFIG_ESP_FLASH_SIZE=4MB
CONFIG_ESP_BOOTLOADER_SIZE=0xF000
CONFIG_ESP_BOOTLOADER_OFFSET=0x0000
CONFIG_ESP_IMAGE0_PRIMARY_START_ADDRESS=0x10000
CONFIG_ESP_APPLICATION_SIZE=0x100000
CONFIG_ESP_IMAGE0_SECONDARY_START_ADDRESS=0x110000
CONFIG_ESP_MCUBOOT_WDT_ENABLE=y
CONFIG_ESP_SCRATCH_OFFSET=0x210000
CONFIG_ESP_SCRATCH_SIZE=0x40000
# When enabled, prevents updating image to an older version
# CONFIG_ESP_DOWNGRADE_PREVENTION=y
# This option makes downgrade prevention rely also on security
# counter (defined using imgtool) instead of only image version
# CONFIG_ESP_DOWNGRADE_PREVENTION_SECURITY_COUNTER=y
# Enables the MCUboot Serial Recovery, that allows the use of
# MCUMGR to upload a firmware through the serial port
# CONFIG_ESP_MCUBOOT_SERIAL=y
# Use sector erasing (recommended) instead of entire image size
# erasing when uploading through Serial Recovery
# CONFIG_ESP_MCUBOOT_ERASE_PROGRESSIVELY=y
# GPIO used to boot on Serial Recovery
# CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT=18
# GPIO input type (0 for Pull-down, 1 for Pull-up)
# CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE=0
# GPIO signal value
# CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL=1
# Delay time for identify the GPIO signal
# CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S=5
# UART port used for serial communication (not needed when using USB)
# CONFIG_ESP_SERIAL_BOOT_UART_NUM=1
# GPIO for Serial RX signal
# CONFIG_ESP_SERIAL_BOOT_GPIO_RX=2
# GPIO for Serial TX signal
# CONFIG_ESP_SERIAL_BOOT_GPIO_TX=3
# Use UART0 for console printing (use either UART or USB alone)
CONFIG_ESP_CONSOLE_UART=y
CONFIG_ESP_CONSOLE_UART_NUM=0
# Configures alternative UART port for console printing
# (UART_NUM=0 must not be changed)
# CONFIG_ESP_CONSOLE_UART_CUSTOM=y
# CONFIG_ESP_CONSOLE_UART_TX_GPIO=3
# CONFIG_ESP_CONSOLE_UART_RX_GPIO=2
# CONFIG_ESP_SIGN_EC256=y
# CONFIG_ESP_SIGN_ED25519=n
# CONFIG_ESP_SIGN_RSA=n
# CONFIG_ESP_SIGN_RSA_LEN=2048
# Use Tinycrypt lib for EC256 or ED25519 signing
# CONFIG_ESP_USE_TINYCRYPT=y
# Use Mbed TLS lib for RSA image signing
# CONFIG_ESP_USE_MBEDTLS=n
# It is strongly recommended to generate a new signing key
# using imgtool instead of use the existent sample
# CONFIG_ESP_SIGN_KEY_FILE=root-ec-p256.pem
# Hardware Secure Boot related options
# CONFIG_SECURE_SIGNED_ON_BOOT=1
# CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME=1
# CONFIG_SECURE_BOOT=1
# CONFIG_SECURE_BOOT_V2_ENABLED=1
# Hardware Flash Encryption related options
# CONFIG_SECURE_FLASH_ENC_ENABLED=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE=1
# CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT=1
# CONFIG_SECURE_BOOT_ALLOW_JTAG=1
# CONFIG_SECURE_BOOT_ALLOW_ROM_BASIC=1
# This option must be also enabled when enabling both Secure Boot
# and Flash Encryption at same time
# CONFIG_SECURE_BOOT_FLASH_ENC_KEYS_BURN_TOGETHER=1
# Options for enabling eFuse emulation in Flash
# CONFIG_EFUSE_VIRTUAL=1
# CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH=1

181
bootloader/mcuboot/boot/espressif/port/esp32c2/ld/bootloader.ld Normal file
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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/** Simplified memory map for the bootloader.
* Make sure the bootloader can load into main memory without overwriting itself.
*
* ESP32-C2 ROM static data usage is as follows:
* - 0x3fccb264 - 0x3fcdcb70: Shared buffers, used in UART/USB/SPI download mode only
* - 0x3fcdcb70 - 0x3fcdeb70: PRO CPU stack, can be reclaimed as heap after RTOS startup
* - 0x3fcdeb70 - 0x3fce0000: ROM .bss and .data (not easily reclaimable)
*
* The 2nd stage bootloader can take space up to the end of ROM shared
* buffers area (0x3fcdcb70).
*/
/* The offset between Dbus and Ibus. Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. */
iram_dram_offset = 0x6e0000;
/* We consider 0x3fcdcb70 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
* and work out iram_seg and iram_loader_seg addresses from there, backwards.
*/
/* These lengths can be adjusted, if necessary: */
bootloader_usable_dram_end = 0x3fcdcb70;
bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
bootloader_dram_seg_len = 0xA000;
bootloader_iram_loader_seg_len = 0x7000;
bootloader_iram_seg_len = 0x8800;
/* Start of the lower region is determined by region size and the end of the higher region */
bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len + iram_dram_offset;
bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
MEMORY
{
iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
}
/* The app may use RAM for static allocations up to the start of iram_loader_seg.
* If you have changed something above and this assert fails:
* 1. Check what the new value of bootloader_iram_loader_seg start is.
* 2. Update the value in this assert.
* 3. Update (SRAM_DRAM_END + I_D_SRAM_OFFSET) in components/esp_system/ld/esp32c2/memory.ld.in to the same value.
*/
ASSERT(bootloader_iram_loader_seg_start == 0x403a9b70, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
/* Default entry point: */
ENTRY(main);
SECTIONS
{
.iram_loader.text :
{
. = ALIGN (16);
_loader_text_start = ABSOLUTE(.);
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
*libhal.a:*.*(.literal .text .literal.* .text.*)
*esp_mcuboot.*(.literal .text .literal.* .text.*)
*esp_loader.*(.literal .text .literal.* .text.*)
*main.*(.literal .text .literal.* .text.*)
*(.fini.literal)
*(.fini)
*(.gnu.version)
_loader_text_end = ABSOLUTE(.);
} > iram_loader_seg
.iram.text :
{
. = ALIGN (16);
*(.entry.text)
*(.init.literal)
*(.init)
} > iram_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
. = ALIGN (8);
_dram_start = ABSOLUTE(.);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
} >dram_seg
.dram0.data :
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
*(.jcr)
_data_end = ABSOLUTE(.);
} >dram_seg
.dram0.rodata :
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
*(.eh_frame)
. = (. + 3) & ~ 3;
/* C++ constructor and destructor tables, properly ordered: */
__init_array_start = ABSOLUTE(.);
KEEP (*crtbegin.*(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__init_array_end = ABSOLUTE(.);
KEEP (*crtbegin.*(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
_rodata_end = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
_dram_end = ABSOLUTE(.);
} >dram_seg
.iram.text :
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram .iram.*) /* catch stray IRAM_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} > iram_seg
}

190
bootloader/mcuboot/boot/espressif/port/esp32c2/serial_adapter.c Normal file
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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <bootutil/bootutil_log.h>
#include <esp_rom_uart.h>
#include <esp_rom_gpio.h>
#include <esp_rom_sys.h>
#include <esp_rom_caps.h>
#include <soc/uart_periph.h>
#include <soc/gpio_struct.h>
#include <soc/io_mux_reg.h>
#include <soc/rtc.h>
#include <hal/gpio_types.h>
#include <hal/gpio_ll.h>
#include <hal/uart_ll.h>
#include <hal/clk_gate_ll.h>
#include <hal/gpio_hal.h>
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT
#define SERIAL_BOOT_GPIO_DETECT CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT
#else
#define SERIAL_BOOT_GPIO_DETECT GPIO_NUM_18
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL
#define SERIAL_BOOT_GPIO_DETECT_VAL CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL
#else
#define SERIAL_BOOT_GPIO_DETECT_VAL 1
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S
#define SERIAL_BOOT_DETECT_DELAY_S CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S
#else
#define SERIAL_BOOT_DETECT_DELAY_S 5
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE
#define SERIAL_BOOT_GPIO_INPUT_TYPE CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE
#else
// pull-down
#define SERIAL_BOOT_GPIO_INPUT_TYPE 0
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_UART_NUM
#define SERIAL_BOOT_UART_NUM CONFIG_ESP_SERIAL_BOOT_UART_NUM
#else
#define SERIAL_BOOT_UART_NUM ESP_ROM_UART_1
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_RX
#define SERIAL_BOOT_GPIO_RX CONFIG_ESP_SERIAL_BOOT_GPIO_RX
#else
#define SERIAL_BOOT_GPIO_RX GPIO_NUM_2
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_TX
#define SERIAL_BOOT_GPIO_TX CONFIG_ESP_SERIAL_BOOT_GPIO_TX
#else
#define SERIAL_BOOT_GPIO_TX GPIO_NUM_3
#endif
static uart_dev_t *serial_boot_uart_dev = (SERIAL_BOOT_UART_NUM == 0) ?
&UART0 :
&UART1;
void console_write(const char *str, int cnt)
{
uint32_t tx_len;
uint32_t write_len;
do {
tx_len = uart_ll_get_txfifo_len(serial_boot_uart_dev);
if (tx_len > 0) {
write_len = tx_len < cnt ? tx_len : cnt;
uart_ll_write_txfifo(serial_boot_uart_dev, (const uint8_t *)str, write_len);
cnt -= write_len;
}
MCUBOOT_WATCHDOG_FEED();
esp_rom_delay_us(1000);
} while (cnt > 0);
}
int console_read(char *str, int cnt, int *newline)
{
uint32_t len = 0;
uint32_t read_len = 0;
bool stop = false;
do {
len = uart_ll_get_rxfifo_len(serial_boot_uart_dev);
if (len > 0) {
for (uint32_t i = 0; i < len; i++) {
/* Read the character from the RX FIFO */
uart_ll_read_rxfifo(serial_boot_uart_dev, (uint8_t *)&str[read_len], 1);
read_len++;
if (read_len == cnt - 1|| str[read_len - 1] == '\n') {
stop = true;
break;
}
}
}
MCUBOOT_WATCHDOG_FEED();
esp_rom_delay_us(1000);
} while (!stop);
*newline = (str[read_len - 1] == '\n') ? 1 : 0;
return read_len;
}
int boot_console_init(void)
{
BOOT_LOG_INF("Initializing serial boot pins");
/* Enable GPIO for UART RX */
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_RX);
esp_rom_gpio_connect_in_signal(SERIAL_BOOT_GPIO_RX,
UART_PERIPH_SIGNAL(SERIAL_BOOT_UART_NUM, SOC_UART_RX_PIN_IDX),
0);
gpio_ll_input_enable(&GPIO, SERIAL_BOOT_GPIO_RX);
esp_rom_gpio_pad_pullup_only(SERIAL_BOOT_GPIO_RX);
/* Enable GPIO for UART TX */
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_TX);
esp_rom_gpio_connect_out_signal(SERIAL_BOOT_GPIO_TX,
UART_PERIPH_SIGNAL(SERIAL_BOOT_UART_NUM, SOC_UART_TX_PIN_IDX),
0, 0);
gpio_ll_output_enable(&GPIO, SERIAL_BOOT_GPIO_TX);
uart_ll_set_sclk(serial_boot_uart_dev, UART_SCLK_DEFAULT);
uart_ll_set_mode_normal(serial_boot_uart_dev);
uart_ll_set_baudrate(serial_boot_uart_dev, 115200, UART_SCLK_DEFAULT);
uart_ll_set_stop_bits(serial_boot_uart_dev, 1u);
uart_ll_set_parity(serial_boot_uart_dev, UART_PARITY_DISABLE);
uart_ll_set_rx_tout(serial_boot_uart_dev, 16);
uart_ll_set_data_bit_num(serial_boot_uart_dev, UART_DATA_8_BITS);
uart_ll_set_tx_idle_num(serial_boot_uart_dev, 0);
uart_ll_set_hw_flow_ctrl(serial_boot_uart_dev, UART_HW_FLOWCTRL_DISABLE, 100);
periph_ll_enable_clk_clear_rst(PERIPH_UART0_MODULE + SERIAL_BOOT_UART_NUM);
uart_ll_txfifo_rst(serial_boot_uart_dev);
uart_ll_rxfifo_rst(serial_boot_uart_dev);
esp_rom_delay_us(50000);
return 0;
}
bool boot_serial_detect_pin(void)
{
bool detected = false;
int pin_value = 0;
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_DETECT);
gpio_ll_input_enable(&GPIO, SERIAL_BOOT_GPIO_DETECT);
switch (SERIAL_BOOT_GPIO_INPUT_TYPE) {
// Pull-down
case 0:
gpio_ll_pulldown_en(&GPIO, SERIAL_BOOT_GPIO_DETECT);
break;
// Pull-up
case 1:
gpio_ll_pullup_en(&GPIO, SERIAL_BOOT_GPIO_DETECT);
break;
}
esp_rom_delay_us(50000);
pin_value = gpio_ll_get_level(&GPIO, SERIAL_BOOT_GPIO_DETECT);
detected = (pin_value == SERIAL_BOOT_GPIO_DETECT_VAL);
esp_rom_delay_us(50000);
if (detected) {
if (SERIAL_BOOT_DETECT_DELAY_S > 0) {
/* The delay time is an approximation */
for (int i = 0; i < (SERIAL_BOOT_DETECT_DELAY_S * 100); i++) {
esp_rom_delay_us(10000);
pin_value = gpio_ll_get_level(&GPIO, SERIAL_BOOT_GPIO_DETECT);
detected = (pin_value == SERIAL_BOOT_GPIO_DETECT_VAL);
if (!detected) {
break;
}
}
}
}
return detected;
}

88
bootloader/mcuboot/boot/espressif/port/esp32c3/bootloader.conf Normal file
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# SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
#
# SPDX-License-Identifier: Apache-2.0
CONFIG_ESP_FLASH_SIZE=4MB
CONFIG_ESP_BOOTLOADER_SIZE=0xF000
CONFIG_ESP_BOOTLOADER_OFFSET=0x0000
CONFIG_ESP_IMAGE0_PRIMARY_START_ADDRESS=0x10000
CONFIG_ESP_APPLICATION_SIZE=0x100000
CONFIG_ESP_IMAGE0_SECONDARY_START_ADDRESS=0x110000
CONFIG_ESP_MCUBOOT_WDT_ENABLE=y
CONFIG_ESP_SCRATCH_OFFSET=0x210000
CONFIG_ESP_SCRATCH_SIZE=0x40000
# When enabled, prevents updating image to an older version
# CONFIG_ESP_DOWNGRADE_PREVENTION=y
# This option makes downgrade prevention rely also on security
# counter (defined using imgtool) instead of only image version
# CONFIG_ESP_DOWNGRADE_PREVENTION_SECURITY_COUNTER=y
# Enables the MCUboot Serial Recovery, that allows the use of
# MCUMGR to upload a firmware through the serial port
# CONFIG_ESP_MCUBOOT_SERIAL=y
# Use Serial through USB JTAG Serial port for Serial Recovery
# CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG=y
# Use sector erasing (recommended) instead of entire image size
# erasing when uploading through Serial Recovery
# CONFIG_ESP_MCUBOOT_ERASE_PROGRESSIVELY=y
# GPIO used to boot on Serial Recovery
# CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT=5
# GPIO input type (0 for Pull-down, 1 for Pull-up)
# CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE=0
# GPIO signal value
# CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL=1
# Delay time for identify the GPIO signal
# CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S=5
# UART port used for serial communication (not needed when using USB)
# CONFIG_ESP_SERIAL_BOOT_UART_NUM=1
# GPIO for Serial RX signal
# CONFIG_ESP_SERIAL_BOOT_GPIO_RX=8
# GPIO for Serial TX signal
# CONFIG_ESP_SERIAL_BOOT_GPIO_TX=9
# Use UART0 for console printing (use either UART or USB alone)
CONFIG_ESP_CONSOLE_UART=y
CONFIG_ESP_CONSOLE_UART_NUM=0
# Configures alternative UART port for console printing
# (UART_NUM=0 must not be changed)
# CONFIG_ESP_CONSOLE_UART_CUSTOM=y
# CONFIG_ESP_CONSOLE_UART_TX_GPIO=9
# CONFIG_ESP_CONSOLE_UART_RX_GPIO=8
# Use USB JTAG Serial for console printing
# CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y
# CONFIG_ESP_SIGN_EC256=y
# CONFIG_ESP_SIGN_ED25519=n
# CONFIG_ESP_SIGN_RSA=n
# CONFIG_ESP_SIGN_RSA_LEN=2048
# Use Tinycrypt lib for EC256 or ED25519 signing
# CONFIG_ESP_USE_TINYCRYPT=y
# Use Mbed TLS lib for RSA image signing
# CONFIG_ESP_USE_MBEDTLS=n
# It is strongly recommended to generate a new signing key
# using imgtool instead of use the existent sample
# CONFIG_ESP_SIGN_KEY_FILE=root-ec-p256.pem
# Hardware Secure Boot related options
# CONFIG_SECURE_SIGNED_ON_BOOT=1
# CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME=1
# CONFIG_SECURE_BOOT=1
# CONFIG_SECURE_BOOT_V2_ENABLED=1
# CONFIG_SECURE_BOOT_SUPPORTS_RSA=1
# Hardware Flash Encryption related options
# CONFIG_SECURE_FLASH_ENC_ENABLED=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE=1
# CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT=1
# CONFIG_SECURE_BOOT_ALLOW_JTAG=1
# CONFIG_SECURE_BOOT_ALLOW_ROM_BASIC=1
# Options for enabling eFuse emulation in Flash
# CONFIG_EFUSE_VIRTUAL=1
# CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH=1

147
bootloader/mcuboot/boot/espressif/port/esp32c3/ld/bootloader.ld Normal file
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/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Simplified memory map for the bootloader.
*
* The main purpose is to make sure the bootloader can load into main memory
* without overwriting itself.
*/
MEMORY
{
iram_seg (RWX) : org = 0x403C7000, len = 0x9000
iram_loader_seg (RWX) : org = 0x403D0000, len = 0x5400
dram_seg (RW) : org = 0x3FCD5400, len = 0xA000
}
/* Default entry point: */
ENTRY(main);
SECTIONS
{
.iram_loader.text :
{
. = ALIGN (16);
_loader_text_start = ABSOLUTE(.);
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
*libhal.a:*.*(.literal .text .literal.* .text.*)
*esp_mcuboot.*(.literal .text .literal.* .text.*)
*esp_loader.*(.literal .text .literal.* .text.*)
*main.*(.literal .text .literal.* .text.*)
*(.fini.literal)
*(.fini)
*(.gnu.version)
_loader_text_end = ABSOLUTE(.);
} > iram_loader_seg
.iram.text :
{
. = ALIGN (16);
*(.entry.text)
*(.init.literal)
*(.init)
} > iram_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
. = ALIGN (8);
_dram_start = ABSOLUTE(.);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
} >dram_seg
.dram0.data :
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
*(.jcr)
_data_end = ABSOLUTE(.);
} >dram_seg
.dram0.rodata :
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
*(.eh_frame)
. = (. + 3) & ~ 3;
/* C++ constructor and destructor tables, properly ordered: */
__init_array_start = ABSOLUTE(.);
KEEP (*crtbegin.*(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__init_array_end = ABSOLUTE(.);
KEEP (*crtbegin.*(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
_rodata_end = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
_dram_end = ABSOLUTE(.);
} >dram_seg
.iram.text :
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram .iram.*) /* catch stray IRAM_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} > iram_seg
}

226
bootloader/mcuboot/boot/espressif/port/esp32c3/serial_adapter.c Normal file
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@@ -0,0 +1,226 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <bootutil/bootutil_log.h>
#include <esp_rom_uart.h>
#include <esp_rom_gpio.h>
#include <esp_rom_sys.h>
#include <esp_rom_caps.h>
#include <soc/uart_periph.h>
#include <soc/gpio_struct.h>
#include <soc/io_mux_reg.h>
#include <soc/rtc.h>
#include <hal/gpio_types.h>
#include <hal/gpio_ll.h>
#include <hal/uart_ll.h>
#include <hal/clk_gate_ll.h>
#include <hal/usb_serial_jtag_ll.h>
#include <hal/gpio_hal.h>
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT
#define SERIAL_BOOT_GPIO_DETECT CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT
#else
#define SERIAL_BOOT_GPIO_DETECT GPIO_NUM_5
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL
#define SERIAL_BOOT_GPIO_DETECT_VAL CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL
#else
#define SERIAL_BOOT_GPIO_DETECT_VAL 1
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S
#define SERIAL_BOOT_DETECT_DELAY_S CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S
#else
#define SERIAL_BOOT_DETECT_DELAY_S 5
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE
#define SERIAL_BOOT_GPIO_INPUT_TYPE CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE
#else
// pull-down
#define SERIAL_BOOT_GPIO_INPUT_TYPE 0
#endif
#ifndef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
#ifdef CONFIG_ESP_SERIAL_BOOT_UART_NUM
#define SERIAL_BOOT_UART_NUM CONFIG_ESP_SERIAL_BOOT_UART_NUM
#else
#define SERIAL_BOOT_UART_NUM ESP_ROM_UART_1
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_RX
#define SERIAL_BOOT_GPIO_RX CONFIG_ESP_SERIAL_BOOT_GPIO_RX
#else
#define SERIAL_BOOT_GPIO_RX GPIO_NUM_8
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_TX
#define SERIAL_BOOT_GPIO_TX CONFIG_ESP_SERIAL_BOOT_GPIO_TX
#else
#define SERIAL_BOOT_GPIO_TX GPIO_NUM_9
#endif
static uart_dev_t *serial_boot_uart_dev = (SERIAL_BOOT_UART_NUM == 0) ?
&UART0 :
&UART1;
#endif
void console_write(const char *str, int cnt)
{
#ifdef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
usb_serial_jtag_ll_txfifo_flush();
while (!usb_serial_jtag_ll_txfifo_writable()) {
MCUBOOT_WATCHDOG_FEED();
}
usb_serial_jtag_ll_write_txfifo((const uint8_t *)str, cnt);
usb_serial_jtag_ll_txfifo_flush();
#else
uint32_t tx_len;
uint32_t write_len;
do {
tx_len = uart_ll_get_txfifo_len(serial_boot_uart_dev);
if (tx_len > 0) {
write_len = tx_len < cnt ? tx_len : cnt;
uart_ll_write_txfifo(serial_boot_uart_dev, (const uint8_t *)str, write_len);
cnt -= write_len;
}
MCUBOOT_WATCHDOG_FEED();
esp_rom_delay_us(1000);
} while (cnt > 0);
#endif
}
int console_read(char *str, int cnt, int *newline)
{
#ifdef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
uint32_t read_len = 0;
esp_rom_delay_us(1000);
do {
if (usb_serial_jtag_ll_rxfifo_data_available()) {
usb_serial_jtag_ll_read_rxfifo((uint8_t *)&str[read_len], 1);
read_len++;
}
MCUBOOT_WATCHDOG_FEED();
esp_rom_delay_us(1000);
} while (!(read_len == cnt || str[read_len - 1] == '\n'));
*newline = (str[read_len - 1] == '\n') ? 1 : 0;
return read_len;
#else
uint32_t len = 0;
uint32_t read_len = 0;
bool stop = false;
do {
len = uart_ll_get_rxfifo_len(serial_boot_uart_dev);
if (len > 0) {
for (uint32_t i = 0; i < len; i++) {
/* Read the character from the RX FIFO */
uart_ll_read_rxfifo(serial_boot_uart_dev, (uint8_t *)&str[read_len], 1);
read_len++;
if (read_len == cnt - 1|| str[read_len - 1] == '\n') {
stop = true;
break;
}
}
}
MCUBOOT_WATCHDOG_FEED();
esp_rom_delay_us(1000);
} while (!stop);
*newline = (str[read_len - 1] == '\n') ? 1 : 0;
return read_len;
#endif
}
int boot_console_init(void)
{
BOOT_LOG_INF("Initializing serial boot pins");
#ifdef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
usb_serial_jtag_ll_txfifo_flush();
esp_rom_uart_tx_wait_idle(0);
#else
/* Enable GPIO for UART RX */
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_RX);
esp_rom_gpio_connect_in_signal(SERIAL_BOOT_GPIO_RX,
UART_PERIPH_SIGNAL(SERIAL_BOOT_UART_NUM, SOC_UART_RX_PIN_IDX),
0);
gpio_ll_input_enable(&GPIO, SERIAL_BOOT_GPIO_RX);
esp_rom_gpio_pad_pullup_only(SERIAL_BOOT_GPIO_RX);
/* Enable GPIO for UART TX */
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_TX);
esp_rom_gpio_connect_out_signal(SERIAL_BOOT_GPIO_TX,
UART_PERIPH_SIGNAL(SERIAL_BOOT_UART_NUM, SOC_UART_TX_PIN_IDX),
0, 0);
gpio_ll_output_enable(&GPIO, SERIAL_BOOT_GPIO_TX);
uart_ll_set_sclk(serial_boot_uart_dev, UART_SCLK_APB);
uart_ll_set_mode_normal(serial_boot_uart_dev);
uart_ll_set_baudrate(serial_boot_uart_dev, 115200, UART_SCLK_APB);
uart_ll_set_stop_bits(serial_boot_uart_dev, 1u);
uart_ll_set_parity(serial_boot_uart_dev, UART_PARITY_DISABLE);
uart_ll_set_rx_tout(serial_boot_uart_dev, 16);
uart_ll_set_data_bit_num(serial_boot_uart_dev, UART_DATA_8_BITS);
uart_ll_set_tx_idle_num(serial_boot_uart_dev, 0);
uart_ll_set_hw_flow_ctrl(serial_boot_uart_dev, UART_HW_FLOWCTRL_DISABLE, 100);
periph_ll_enable_clk_clear_rst(PERIPH_UART0_MODULE + SERIAL_BOOT_UART_NUM);
uart_ll_txfifo_rst(serial_boot_uart_dev);
uart_ll_rxfifo_rst(serial_boot_uart_dev);
esp_rom_delay_us(50000);
#endif
return 0;
}
bool boot_serial_detect_pin(void)
{
bool detected = false;
int pin_value = 0;
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_DETECT);
gpio_ll_input_enable(&GPIO, SERIAL_BOOT_GPIO_DETECT);
switch (SERIAL_BOOT_GPIO_INPUT_TYPE) {
// Pull-down
case 0:
gpio_ll_pulldown_en(&GPIO, SERIAL_BOOT_GPIO_DETECT);
break;
// Pull-up
case 1:
gpio_ll_pullup_en(&GPIO, SERIAL_BOOT_GPIO_DETECT);
break;
}
esp_rom_delay_us(50000);
pin_value = gpio_ll_get_level(&GPIO, SERIAL_BOOT_GPIO_DETECT);
detected = (pin_value == SERIAL_BOOT_GPIO_DETECT_VAL);
esp_rom_delay_us(50000);
if (detected) {
if (SERIAL_BOOT_DETECT_DELAY_S > 0) {
/* The delay time is an approximation */
for (int i = 0; i < (SERIAL_BOOT_DETECT_DELAY_S * 100); i++) {
esp_rom_delay_us(10000);
pin_value = gpio_ll_get_level(&GPIO, SERIAL_BOOT_GPIO_DETECT);
detected = (pin_value == SERIAL_BOOT_GPIO_DETECT_VAL);
if (!detected) {
break;
}
}
}
}
return detected;
}

88
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# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
#
# SPDX-License-Identifier: Apache-2.0
CONFIG_ESP_FLASH_SIZE=4MB
CONFIG_ESP_BOOTLOADER_SIZE=0xF000
CONFIG_ESP_BOOTLOADER_OFFSET=0x0000
CONFIG_ESP_IMAGE0_PRIMARY_START_ADDRESS=0x10000
CONFIG_ESP_APPLICATION_SIZE=0x100000
CONFIG_ESP_IMAGE0_SECONDARY_START_ADDRESS=0x110000
CONFIG_ESP_MCUBOOT_WDT_ENABLE=y
CONFIG_ESP_SCRATCH_OFFSET=0x210000
CONFIG_ESP_SCRATCH_SIZE=0x40000
# When enabled, prevents updating image to an older version
# CONFIG_ESP_DOWNGRADE_PREVENTION=y
# This option makes downgrade prevention rely also on security
# counter (defined using imgtool) instead of only image version
# CONFIG_ESP_DOWNGRADE_PREVENTION_SECURITY_COUNTER=y
# Enables the MCUboot Serial Recovery, that allows the use of
# MCUMGR to upload a firmware through the serial port
# CONFIG_ESP_MCUBOOT_SERIAL=y
# Use Serial through USB JTAG Serial port for Serial Recovery
# CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG=y
# Use sector erasing (recommended) instead of entire image size
# erasing when uploading through Serial Recovery
# CONFIG_ESP_MCUBOOT_ERASE_PROGRESSIVELY=y
# GPIO used to boot on Serial Recovery
# CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT=5
# GPIO input type (0 for Pull-down, 1 for Pull-up)
# CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE=0
# GPIO signal value
# CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL=1
# Delay time for identify the GPIO signal
# CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S=5
# UART port used for serial communication (not needed when using USB)
# CONFIG_ESP_SERIAL_BOOT_UART_NUM=1
# GPIO for Serial RX signal
# CONFIG_ESP_SERIAL_BOOT_GPIO_RX=8
# GPIO for Serial TX signal
# CONFIG_ESP_SERIAL_BOOT_GPIO_TX=9
# Use UART0 for console printing (use either UART or USB alone)
CONFIG_ESP_CONSOLE_UART=y
CONFIG_ESP_CONSOLE_UART_NUM=0
# Configures alternative UART port for console printing
# (UART_NUM=0 must not be changed)
# CONFIG_ESP_CONSOLE_UART_CUSTOM=y
# CONFIG_ESP_CONSOLE_UART_TX_GPIO=9
# CONFIG_ESP_CONSOLE_UART_RX_GPIO=8
# Use USB JTAG Serial for console printing
# CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y
# CONFIG_ESP_SIGN_EC256=y
# CONFIG_ESP_SIGN_ED25519=n
# CONFIG_ESP_SIGN_RSA=n
# CONFIG_ESP_SIGN_RSA_LEN=2048
# Use Tinycrypt lib for EC256 or ED25519 signing
# CONFIG_ESP_USE_TINYCRYPT=y
# Use Mbed TLS lib for RSA image signing
# CONFIG_ESP_USE_MBEDTLS=n
# It is strongly recommended to generate a new signing key
# using imgtool instead of use the existent sample
# CONFIG_ESP_SIGN_KEY_FILE=root-ec-p256.pem
# Hardware Secure Boot related options
# CONFIG_SECURE_SIGNED_ON_BOOT=1
# CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME=1
# CONFIG_SECURE_BOOT=1
# CONFIG_SECURE_BOOT_V2_ENABLED=1
# CONFIG_SECURE_BOOT_SUPPORTS_RSA=1
# Hardware Flash Encryption related options
# CONFIG_SECURE_FLASH_ENC_ENABLED=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE=1
# CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT=1
# CONFIG_SECURE_BOOT_ALLOW_JTAG=1
# CONFIG_SECURE_BOOT_ALLOW_ROM_BASIC=1
# Options for enabling eFuse emulation in Flash
# CONFIG_EFUSE_VIRTUAL=1
# CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH=1

177
bootloader/mcuboot/boot/espressif/port/esp32c6/ld/bootloader.ld Normal file
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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/** Simplified memory map for the bootloader.
* Make sure the bootloader can load into main memory without overwriting itself.
*
* ESP32-C6 ROM static data usage is as follows:
* - 0x4086ad08 - 0x4087c610: Shared buffers, used in UART/USB/SPI download mode only
* - 0x4087c610 - 0x4087e610: PRO CPU stack, can be reclaimed as heap after RTOS startup
* - 0x4087e610 - 0x40880000: ROM .bss and .data (not easily reclaimable)
*
* The 2nd stage bootloader can take space up to the end of ROM shared
* buffers area (0x4087c610).
*/
/* We consider 0x4087c610 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
* and work out iram_seg and iram_loader_seg addresses from there, backwards.
*/
/* These lengths can be adjusted, if necessary: */
bootloader_usable_dram_end = 0x4087c610;
bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
bootloader_dram_seg_len = 0xA000;
bootloader_iram_loader_seg_len = 0x7000;
bootloader_iram_seg_len = 0x9000;
/* Start of the lower region is determined by region size and the end of the higher region */
bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead; /* 0x4087c610 - 0x2000 = 0x4087a610 */
bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len; /* 0x4087a610 - 0x5000 = 0x40875610 */
bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len; /* 0x40875610 - 0x7000 = 0x4086e610 */
bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len; /* 0x4086e610 - 0x3000 = 0x4086b610 */
MEMORY
{
iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
}
/* The app may use RAM for static allocations up to the start of iram_loader_seg.
* If you have changed something above and this assert fails:
* 1. Check what the new value of bootloader_iram_loader_seg start is.
* 2. Update the value in this assert.
* 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c6/memory.ld.in to the same value.
*/
ASSERT(bootloader_iram_loader_seg_start == 0x40869610, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
/* Default entry point: */
ENTRY(main);
SECTIONS
{
.iram_loader.text :
{
. = ALIGN (16);
_loader_text_start = ABSOLUTE(.);
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
*libhal.a:*.*(.literal .text .literal.* .text.*)
*esp_mcuboot.*(.literal .text .literal.* .text.*)
*esp_loader.*(.literal .text .literal.* .text.*)
*main.*(.literal .text .literal.* .text.*)
*(.fini.literal)
*(.fini)
*(.gnu.version)
_loader_text_end = ABSOLUTE(.);
} > iram_loader_seg
.iram.text :
{
. = ALIGN (16);
*(.entry.text)
*(.init.literal)
*(.init)
} > iram_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
. = ALIGN (8);
_dram_start = ABSOLUTE(.);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
} >dram_seg
.dram0.data :
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
*(.jcr)
_data_end = ABSOLUTE(.);
} >dram_seg
.dram0.rodata :
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
*(.eh_frame)
. = (. + 3) & ~ 3;
/* C++ constructor and destructor tables, properly ordered: */
__init_array_start = ABSOLUTE(.);
KEEP (*crtbegin.*(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__init_array_end = ABSOLUTE(.);
KEEP (*crtbegin.*(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
_rodata_end = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
_dram_end = ABSOLUTE(.);
} >dram_seg
.iram.text :
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram .iram.*) /* catch stray IRAM_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} > iram_seg
}

226
bootloader/mcuboot/boot/espressif/port/esp32c6/serial_adapter.c Normal file
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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <bootutil/bootutil_log.h>
#include <esp_rom_uart.h>
#include <esp_rom_gpio.h>
#include <esp_rom_sys.h>
#include <esp_rom_caps.h>
#include <soc/uart_periph.h>
#include <soc/gpio_struct.h>
#include <soc/io_mux_reg.h>
#include <soc/rtc.h>
#include <hal/gpio_types.h>
#include <hal/gpio_ll.h>
#include <hal/uart_ll.h>
#include <hal/clk_gate_ll.h>
#include <hal/usb_serial_jtag_ll.h>
#include <hal/gpio_hal.h>
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT
#define SERIAL_BOOT_GPIO_DETECT CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT
#else
#define SERIAL_BOOT_GPIO_DETECT GPIO_NUM_3
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL
#define SERIAL_BOOT_GPIO_DETECT_VAL CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL
#else
#define SERIAL_BOOT_GPIO_DETECT_VAL 1
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S
#define SERIAL_BOOT_DETECT_DELAY_S CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S
#else
#define SERIAL_BOOT_DETECT_DELAY_S 5
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE
#define SERIAL_BOOT_GPIO_INPUT_TYPE CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE
#else
// pull-down
#define SERIAL_BOOT_GPIO_INPUT_TYPE 0
#endif
#ifndef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
#ifdef CONFIG_ESP_SERIAL_BOOT_UART_NUM
#define SERIAL_BOOT_UART_NUM CONFIG_ESP_SERIAL_BOOT_UART_NUM
#else
#define SERIAL_BOOT_UART_NUM ESP_ROM_UART_1
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_RX
#define SERIAL_BOOT_GPIO_RX CONFIG_ESP_SERIAL_BOOT_GPIO_RX
#else
#define SERIAL_BOOT_GPIO_RX GPIO_NUM_10
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_TX
#define SERIAL_BOOT_GPIO_TX CONFIG_ESP_SERIAL_BOOT_GPIO_TX
#else
#define SERIAL_BOOT_GPIO_TX GPIO_NUM_11
#endif
static uart_dev_t *serial_boot_uart_dev = (SERIAL_BOOT_UART_NUM == 0) ?
&UART0 :
&UART1;
#endif
void console_write(const char *str, int cnt)
{
#ifdef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
usb_serial_jtag_ll_txfifo_flush();
while (!usb_serial_jtag_ll_txfifo_writable()) {
MCUBOOT_WATCHDOG_FEED();
}
usb_serial_jtag_ll_write_txfifo((const uint8_t *)str, cnt);
usb_serial_jtag_ll_txfifo_flush();
#else
uint32_t tx_len;
uint32_t write_len;
do {
tx_len = uart_ll_get_txfifo_len(serial_boot_uart_dev);
if (tx_len > 0) {
write_len = tx_len < cnt ? tx_len : cnt;
uart_ll_write_txfifo(serial_boot_uart_dev, (const uint8_t *)str, write_len);
cnt -= write_len;
}
MCUBOOT_WATCHDOG_FEED();
esp_rom_delay_us(1000);
} while (cnt > 0);
#endif
}
int console_read(char *str, int cnt, int *newline)
{
#ifdef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
uint32_t read_len = 0;
esp_rom_delay_us(1000);
do {
if (usb_serial_jtag_ll_rxfifo_data_available()) {
usb_serial_jtag_ll_read_rxfifo((uint8_t *)&str[read_len], 1);
read_len++;
}
MCUBOOT_WATCHDOG_FEED();
esp_rom_delay_us(1000);
} while (!(read_len == cnt || str[read_len - 1] == '\n'));
*newline = (str[read_len - 1] == '\n') ? 1 : 0;
return read_len;
#else
uint32_t len = 0;
uint32_t read_len = 0;
bool stop = false;
do {
len = uart_ll_get_rxfifo_len(serial_boot_uart_dev);
if (len > 0) {
for (uint32_t i = 0; i < len; i++) {
/* Read the character from the RX FIFO */
uart_ll_read_rxfifo(serial_boot_uart_dev, (uint8_t *)&str[read_len], 1);
read_len++;
if (read_len == cnt - 1|| str[read_len - 1] == '\n') {
stop = true;
break;
}
}
}
MCUBOOT_WATCHDOG_FEED();
esp_rom_delay_us(1000);
} while (!stop);
*newline = (str[read_len - 1] == '\n') ? 1 : 0;
return read_len;
#endif
}
int boot_console_init(void)
{
BOOT_LOG_INF("Initializing serial boot pins");
#ifdef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
usb_serial_jtag_ll_txfifo_flush();
esp_rom_uart_tx_wait_idle(0);
#else
/* Enable GPIO for UART RX */
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_RX);
esp_rom_gpio_connect_in_signal(SERIAL_BOOT_GPIO_RX,
UART_PERIPH_SIGNAL(SERIAL_BOOT_UART_NUM, SOC_UART_RX_PIN_IDX),
0);
gpio_ll_input_enable(&GPIO, SERIAL_BOOT_GPIO_RX);
esp_rom_gpio_pad_pullup_only(SERIAL_BOOT_GPIO_RX);
/* Enable GPIO for UART TX */
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_TX);
esp_rom_gpio_connect_out_signal(SERIAL_BOOT_GPIO_TX,
UART_PERIPH_SIGNAL(SERIAL_BOOT_UART_NUM, SOC_UART_TX_PIN_IDX),
0, 0);
gpio_ll_output_enable(&GPIO, SERIAL_BOOT_GPIO_TX);
uart_ll_set_sclk(serial_boot_uart_dev, UART_SCLK_DEFAULT);
uart_ll_set_mode_normal(serial_boot_uart_dev);
uart_ll_set_baudrate(serial_boot_uart_dev, 115200, UART_SCLK_DEFAULT);
uart_ll_set_stop_bits(serial_boot_uart_dev, 1u);
uart_ll_set_parity(serial_boot_uart_dev, UART_PARITY_DISABLE);
uart_ll_set_rx_tout(serial_boot_uart_dev, 16);
uart_ll_set_data_bit_num(serial_boot_uart_dev, UART_DATA_8_BITS);
uart_ll_set_tx_idle_num(serial_boot_uart_dev, 0);
uart_ll_set_hw_flow_ctrl(serial_boot_uart_dev, UART_HW_FLOWCTRL_DISABLE, 100);
periph_ll_enable_clk_clear_rst(PERIPH_UART0_MODULE + SERIAL_BOOT_UART_NUM);
uart_ll_txfifo_rst(serial_boot_uart_dev);
uart_ll_rxfifo_rst(serial_boot_uart_dev);
esp_rom_delay_us(50000);
#endif
return 0;
}
bool boot_serial_detect_pin(void)
{
bool detected = false;
int pin_value = 0;
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_DETECT);
gpio_ll_input_enable(&GPIO, SERIAL_BOOT_GPIO_DETECT);
switch (SERIAL_BOOT_GPIO_INPUT_TYPE) {
// Pull-down
case 0:
gpio_ll_pulldown_en(&GPIO, SERIAL_BOOT_GPIO_DETECT);
break;
// Pull-up
case 1:
gpio_ll_pullup_en(&GPIO, SERIAL_BOOT_GPIO_DETECT);
break;
}
esp_rom_delay_us(50000);
pin_value = gpio_ll_get_level(&GPIO, SERIAL_BOOT_GPIO_DETECT);
detected = (pin_value == SERIAL_BOOT_GPIO_DETECT_VAL);
esp_rom_delay_us(50000);
if (detected) {
if (SERIAL_BOOT_DETECT_DELAY_S > 0) {
/* The delay time is an approximation */
for (int i = 0; i < (SERIAL_BOOT_DETECT_DELAY_S * 100); i++) {
esp_rom_delay_us(10000);
pin_value = gpio_ll_get_level(&GPIO, SERIAL_BOOT_GPIO_DETECT);
detected = (pin_value == SERIAL_BOOT_GPIO_DETECT_VAL);
if (!detected) {
break;
}
}
}
}
return detected;
}

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bootloader/mcuboot/boot/espressif/port/esp32h2/bootloader.conf Normal file
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# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
#
# SPDX-License-Identifier: Apache-2.0
CONFIG_ESP_FLASH_SIZE=4MB
CONFIG_ESP_BOOTLOADER_SIZE=0xF000
CONFIG_ESP_BOOTLOADER_OFFSET=0x0000
CONFIG_ESP_IMAGE0_PRIMARY_START_ADDRESS=0x10000
CONFIG_ESP_APPLICATION_SIZE=0x100000
CONFIG_ESP_IMAGE0_SECONDARY_START_ADDRESS=0x110000
CONFIG_ESP_MCUBOOT_WDT_ENABLE=y
CONFIG_ESP_SCRATCH_OFFSET=0x210000
CONFIG_ESP_SCRATCH_SIZE=0x40000
# When enabled, prevents updating image to an older version
# CONFIG_ESP_DOWNGRADE_PREVENTION=y
# This option makes downgrade prevention rely also on security
# counter (defined using imgtool) instead of only image version
# CONFIG_ESP_DOWNGRADE_PREVENTION_SECURITY_COUNTER=y
# Enables the MCUboot Serial Recovery, that allows the use of
# MCUMGR to upload a firmware through the serial port
# CONFIG_ESP_MCUBOOT_SERIAL=y
# Use Serial through USB JTAG Serial port for Serial Recovery
# CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG=y
# Use sector erasing (recommended) instead of entire image size
# erasing when uploading through Serial Recovery
# CONFIG_ESP_MCUBOOT_ERASE_PROGRESSIVELY=y
# GPIO used to boot on Serial Recovery
# CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT=5
# GPIO input type (0 for Pull-down, 1 for Pull-up)
# CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE=0
# GPIO signal value
# CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL=1
# Delay time for identify the GPIO signal
# CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S=5
# UART port used for serial communication (not needed when using USB)
# CONFIG_ESP_SERIAL_BOOT_UART_NUM=1
# GPIO for Serial RX signal
# CONFIG_ESP_SERIAL_BOOT_GPIO_RX=8
# GPIO for Serial TX signal
# CONFIG_ESP_SERIAL_BOOT_GPIO_TX=9
# Use UART0 for console printing (use either UART or USB alone)
CONFIG_ESP_CONSOLE_UART=y
CONFIG_ESP_CONSOLE_UART_NUM=0
# Configures alternative UART port for console printing
# (UART_NUM=0 must not be changed)
# CONFIG_ESP_CONSOLE_UART_CUSTOM=y
# CONFIG_ESP_CONSOLE_UART_TX_GPIO=9
# CONFIG_ESP_CONSOLE_UART_RX_GPIO=8
# Use USB JTAG Serial for console printing
# CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y
# CONFIG_ESP_SIGN_EC256=y
# CONFIG_ESP_SIGN_ED25519=n
# CONFIG_ESP_SIGN_RSA=n
# CONFIG_ESP_SIGN_RSA_LEN=2048
# Use Tinycrypt lib for EC256 or ED25519 signing
# CONFIG_ESP_USE_TINYCRYPT=y
# Use Mbed TLS lib for RSA image signing
# CONFIG_ESP_USE_MBEDTLS=n
# It is strongly recommended to generate a new signing key
# using imgtool instead of use the existent sample
# CONFIG_ESP_SIGN_KEY_FILE=root-ec-p256.pem
# Hardware Secure Boot related options
# CONFIG_SECURE_SIGNED_ON_BOOT=1
# CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME=1
# CONFIG_SECURE_BOOT=1
# CONFIG_SECURE_BOOT_V2_ENABLED=1
# CONFIG_SECURE_BOOT_SUPPORTS_RSA=1
# Hardware Flash Encryption related options
# CONFIG_SECURE_FLASH_ENC_ENABLED=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE=1
# CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT=1
# CONFIG_SECURE_BOOT_ALLOW_JTAG=1
# CONFIG_SECURE_BOOT_ALLOW_ROM_BASIC=1
# Options for enabling eFuse emulation in Flash
# CONFIG_EFUSE_VIRTUAL=1
# CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH=1

179
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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/** Simplified memory map for the bootloader.
* Make sure the bootloader can load into main memory without overwriting itself.
*
* ESP32-H2 ROM static data usage is as follows:
* - 0x4083ba78 - 0x4084d380: Shared buffers, used in UART/USB/SPI download mode only
* - 0x4084d380 - 0x4084f380: PRO CPU stack, can be reclaimed as heap after RTOS startup
* - 0x4084f380 - 0x4084fee0: ROM .bss and .data used in startup code or nonos/early boot (can be freed when IDF runs)
* - 0x4084fee0 - 0x40850000: ROM .bss and .data used in startup code and when IDF runs (cannot be freed)
*
* The 2nd stage bootloader can take space up to the end of ROM shared
* buffers area (0x4084d380).
*/
/* We consider 0x3fcdc710 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
* and work out iram_seg and iram_loader_seg addresses from there, backwards.
*/
/* These lengths can be adjusted, if necessary: */
bootloader_usable_dram_end = 0x4084cfd0;
bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
bootloader_dram_seg_len = 0xA000;
bootloader_iram_loader_seg_len = 0x7000;
bootloader_iram_seg_len = 0x8800;
/* Start of the lower region is determined by region size and the end of the higher region */
bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len;
bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
MEMORY
{
iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
}
/* The app may use RAM for static allocations up to the start of iram_loader_seg.
* If you have changed something above and this assert fails:
* 1. Check what the new value of bootloader_iram_loader_seg start is.
* 2. Update the value in this assert.
* 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32h2/memory.ld.in to the same value.
*/
ASSERT(bootloader_iram_loader_seg_start == 0x40839FD0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
/* Default entry point: */
ENTRY(main);
SECTIONS
{
.iram_loader.text :
{
. = ALIGN (16);
_loader_text_start = ABSOLUTE(.);
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
*libhal.a:*.*(.literal .text .literal.* .text.*)
*esp_mcuboot.*(.literal .text .literal.* .text.*)
*esp_loader.*(.literal .text .literal.* .text.*)
*main.*(.literal .text .literal.* .text.*)
*(.fini.literal)
*(.fini)
*(.gnu.version)
_loader_text_end = ABSOLUTE(.);
} > iram_loader_seg
.iram.text :
{
. = ALIGN (16);
*(.entry.text)
*(.init.literal)
*(.init)
} > iram_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
. = ALIGN (8);
_dram_start = ABSOLUTE(.);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
} >dram_seg
.dram0.data :
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
*(.jcr)
_data_end = ABSOLUTE(.);
} >dram_seg
.dram0.rodata :
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
*(.eh_frame)
. = (. + 3) & ~ 3;
/* C++ constructor and destructor tables, properly ordered: */
__init_array_start = ABSOLUTE(.);
KEEP (*crtbegin.*(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__init_array_end = ABSOLUTE(.);
KEEP (*crtbegin.*(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
_rodata_end = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
_dram_end = ABSOLUTE(.);
} >dram_seg
.iram.text :
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram .iram.*) /* catch stray IRAM_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} > iram_seg
}

226
bootloader/mcuboot/boot/espressif/port/esp32h2/serial_adapter.c Normal file
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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <bootutil/bootutil_log.h>
#include <esp_rom_uart.h>
#include <esp_rom_gpio.h>
#include <esp_rom_sys.h>
#include <esp_rom_caps.h>
#include <soc/uart_periph.h>
#include <soc/gpio_struct.h>
#include <soc/io_mux_reg.h>
#include <soc/rtc.h>
#include <hal/gpio_types.h>
#include <hal/gpio_ll.h>
#include <hal/uart_ll.h>
#include <hal/clk_gate_ll.h>
#include <hal/usb_serial_jtag_ll.h>
#include <hal/gpio_hal.h>
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT
#define SERIAL_BOOT_GPIO_DETECT CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT
#else
#define SERIAL_BOOT_GPIO_DETECT GPIO_NUM_12
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL
#define SERIAL_BOOT_GPIO_DETECT_VAL CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL
#else
#define SERIAL_BOOT_GPIO_DETECT_VAL 1
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S
#define SERIAL_BOOT_DETECT_DELAY_S CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S
#else
#define SERIAL_BOOT_DETECT_DELAY_S 5
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE
#define SERIAL_BOOT_GPIO_INPUT_TYPE CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE
#else
// pull-down
#define SERIAL_BOOT_GPIO_INPUT_TYPE 0
#endif
#ifndef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
#ifdef CONFIG_ESP_SERIAL_BOOT_UART_NUM
#define SERIAL_BOOT_UART_NUM CONFIG_ESP_SERIAL_BOOT_UART_NUM
#else
#define SERIAL_BOOT_UART_NUM ESP_ROM_UART_1
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_RX
#define SERIAL_BOOT_GPIO_RX CONFIG_ESP_SERIAL_BOOT_GPIO_RX
#else
#define SERIAL_BOOT_GPIO_RX GPIO_NUM_10
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_TX
#define SERIAL_BOOT_GPIO_TX CONFIG_ESP_SERIAL_BOOT_GPIO_TX
#else
#define SERIAL_BOOT_GPIO_TX GPIO_NUM_11
#endif
static uart_dev_t *serial_boot_uart_dev = (SERIAL_BOOT_UART_NUM == 0) ?
&UART0 :
&UART1;
#endif
void console_write(const char *str, int cnt)
{
#ifdef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
usb_serial_jtag_ll_txfifo_flush();
while (!usb_serial_jtag_ll_txfifo_writable()) {
MCUBOOT_WATCHDOG_FEED();
}
usb_serial_jtag_ll_write_txfifo((const uint8_t *)str, cnt);
usb_serial_jtag_ll_txfifo_flush();
#else
uint32_t tx_len;
uint32_t write_len;
do {
tx_len = uart_ll_get_txfifo_len(serial_boot_uart_dev);
if (tx_len > 0) {
write_len = tx_len < cnt ? tx_len : cnt;
uart_ll_write_txfifo(serial_boot_uart_dev, (const uint8_t *)str, write_len);
cnt -= write_len;
}
MCUBOOT_WATCHDOG_FEED();
esp_rom_delay_us(1000);
} while (cnt > 0);
#endif
}
int console_read(char *str, int cnt, int *newline)
{
#ifdef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
uint32_t read_len = 0;
esp_rom_delay_us(1000);
do {
if (usb_serial_jtag_ll_rxfifo_data_available()) {
usb_serial_jtag_ll_read_rxfifo((uint8_t *)&str[read_len], 1);
read_len++;
}
MCUBOOT_WATCHDOG_FEED();
esp_rom_delay_us(1000);
} while (!(read_len == cnt || str[read_len - 1] == '\n'));
*newline = (str[read_len - 1] == '\n') ? 1 : 0;
return read_len;
#else
uint32_t len = 0;
uint32_t read_len = 0;
bool stop = false;
do {
len = uart_ll_get_rxfifo_len(serial_boot_uart_dev);
if (len > 0) {
for (uint32_t i = 0; i < len; i++) {
/* Read the character from the RX FIFO */
uart_ll_read_rxfifo(serial_boot_uart_dev, (uint8_t *)&str[read_len], 1);
read_len++;
if (read_len == cnt - 1|| str[read_len - 1] == '\n') {
stop = true;
break;
}
}
}
MCUBOOT_WATCHDOG_FEED();
esp_rom_delay_us(1000);
} while (!stop);
*newline = (str[read_len - 1] == '\n') ? 1 : 0;
return read_len;
#endif
}
int boot_console_init(void)
{
BOOT_LOG_INF("Initializing serial boot pins");
#ifdef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
usb_serial_jtag_ll_txfifo_flush();
esp_rom_uart_tx_wait_idle(0);
#else
/* Enable GPIO for UART RX */
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_RX);
esp_rom_gpio_connect_in_signal(SERIAL_BOOT_GPIO_RX,
UART_PERIPH_SIGNAL(SERIAL_BOOT_UART_NUM, SOC_UART_RX_PIN_IDX),
0);
gpio_ll_input_enable(&GPIO, SERIAL_BOOT_GPIO_RX);
esp_rom_gpio_pad_pullup_only(SERIAL_BOOT_GPIO_RX);
/* Enable GPIO for UART TX */
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_TX);
esp_rom_gpio_connect_out_signal(SERIAL_BOOT_GPIO_TX,
UART_PERIPH_SIGNAL(SERIAL_BOOT_UART_NUM, SOC_UART_TX_PIN_IDX),
0, 0);
gpio_ll_output_enable(&GPIO, SERIAL_BOOT_GPIO_TX);
uart_ll_set_sclk(serial_boot_uart_dev, UART_SCLK_DEFAULT);
uart_ll_set_mode_normal(serial_boot_uart_dev);
uart_ll_set_baudrate(serial_boot_uart_dev, 115200, UART_SCLK_DEFAULT);
uart_ll_set_stop_bits(serial_boot_uart_dev, 1u);
uart_ll_set_parity(serial_boot_uart_dev, UART_PARITY_DISABLE);
uart_ll_set_rx_tout(serial_boot_uart_dev, 16);
uart_ll_set_data_bit_num(serial_boot_uart_dev, UART_DATA_8_BITS);
uart_ll_set_tx_idle_num(serial_boot_uart_dev, 0);
uart_ll_set_hw_flow_ctrl(serial_boot_uart_dev, UART_HW_FLOWCTRL_DISABLE, 100);
periph_ll_enable_clk_clear_rst(PERIPH_UART0_MODULE + SERIAL_BOOT_UART_NUM);
uart_ll_txfifo_rst(serial_boot_uart_dev);
uart_ll_rxfifo_rst(serial_boot_uart_dev);
esp_rom_delay_us(50000);
#endif
return 0;
}
bool boot_serial_detect_pin(void)
{
bool detected = false;
int pin_value = 0;
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_DETECT);
gpio_ll_input_enable(&GPIO, SERIAL_BOOT_GPIO_DETECT);
switch (SERIAL_BOOT_GPIO_INPUT_TYPE) {
// Pull-down
case 0:
gpio_ll_pulldown_en(&GPIO, SERIAL_BOOT_GPIO_DETECT);
break;
// Pull-up
case 1:
gpio_ll_pullup_en(&GPIO, SERIAL_BOOT_GPIO_DETECT);
break;
}
esp_rom_delay_us(50000);
pin_value = gpio_ll_get_level(&GPIO, SERIAL_BOOT_GPIO_DETECT);
detected = (pin_value == SERIAL_BOOT_GPIO_DETECT_VAL);
esp_rom_delay_us(50000);
if (detected) {
if (SERIAL_BOOT_DETECT_DELAY_S > 0) {
/* The delay time is an approximation */
for (int i = 0; i < (SERIAL_BOOT_DETECT_DELAY_S * 100); i++) {
esp_rom_delay_us(10000);
pin_value = gpio_ll_get_level(&GPIO, SERIAL_BOOT_GPIO_DETECT);
detected = (pin_value == SERIAL_BOOT_GPIO_DETECT_VAL);
if (!detected) {
break;
}
}
}
}
return detected;
}

84
bootloader/mcuboot/boot/espressif/port/esp32s2/bootloader.conf Normal file
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# SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
#
# SPDX-License-Identifier: Apache-2.0
CONFIG_ESP_FLASH_SIZE=4MB
CONFIG_ESP_BOOTLOADER_SIZE=0xF000
CONFIG_ESP_BOOTLOADER_OFFSET=0x1000
CONFIG_ESP_IMAGE0_PRIMARY_START_ADDRESS=0x10000
CONFIG_ESP_APPLICATION_SIZE=0x100000
CONFIG_ESP_IMAGE0_SECONDARY_START_ADDRESS=0x110000
CONFIG_ESP_MCUBOOT_WDT_ENABLE=y
CONFIG_ESP_SCRATCH_OFFSET=0x210000
CONFIG_ESP_SCRATCH_SIZE=0x40000
# When enabled, prevents updating image to an older version
# CONFIG_ESP_DOWNGRADE_PREVENTION=y
# This option makes downgrade prevention rely also on security
# counter (defined using imgtool) instead of only image version
# CONFIG_ESP_DOWNGRADE_PREVENTION_SECURITY_COUNTER=y
# Enables the MCUboot Serial Recovery, that allows the use of
# MCUMGR to upload a firmware through the serial port
# CONFIG_ESP_MCUBOOT_SERIAL=y
# Use sector erasing (recommended) instead of entire image size
# erasing when uploading through Serial Recovery
# CONFIG_ESP_MCUBOOT_ERASE_PROGRESSIVELY=y
# GPIO used to boot on Serial Recovery
# CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT=5
# GPIO input type (0 for Pull-down, 1 for Pull-up)
# CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE=0
# GPIO signal value
# CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL=1
# Delay time for identify the GPIO signal
# CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S=5
# UART port used for serial communication (not needed when using USB)
# CONFIG_ESP_SERIAL_BOOT_UART_NUM=1
# GPIO for Serial RX signal
# CONFIG_ESP_SERIAL_BOOT_GPIO_RX=18
# GPIO for Serial TX signal
# CONFIG_ESP_SERIAL_BOOT_GPIO_TX=17
# Use UART0 for console printing (use either UART or USB alone)
CONFIG_ESP_CONSOLE_UART=y
CONFIG_ESP_CONSOLE_UART_NUM=0
# Configures alternative UART port for console printing
# (UART_NUM=0 must not be changed)
# CONFIG_ESP_CONSOLE_UART_CUSTOM=y
# CONFIG_ESP_CONSOLE_UART_TX_GPIO=17
# CONFIG_ESP_CONSOLE_UART_RX_GPIO=18
# CONFIG_ESP_SIGN_EC256=y
# CONFIG_ESP_SIGN_ED25519=n
# CONFIG_ESP_SIGN_RSA=n
# CONFIG_ESP_SIGN_RSA_LEN=2048
# Use Tinycrypt lib for EC256 or ED25519 signing
# CONFIG_ESP_USE_TINYCRYPT=y
# Use Mbed TLS lib for RSA image signing
# CONFIG_ESP_USE_MBEDTLS=n
# It is strongly recommended to generate a new signing key
# using imgtool instead of use the existent sample
# CONFIG_ESP_SIGN_KEY_FILE=root-ec-p256.pem
# Hardware Secure Boot related options
# CONFIG_SECURE_SIGNED_ON_BOOT=1
# CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME=1
# CONFIG_SECURE_BOOT=1
# CONFIG_SECURE_BOOT_V2_ENABLED=1
# CONFIG_SECURE_BOOT_SUPPORTS_RSA=1
# Hardware Flash Encryption related options
# CONFIG_SECURE_FLASH_ENC_ENABLED=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE=1
# CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT=1
# CONFIG_SECURE_BOOT_ALLOW_JTAG=1
# CONFIG_SECURE_BOOT_ALLOW_ROM_BASIC=1
# Options for enabling eFuse emulation in Flash
# CONFIG_EFUSE_VIRTUAL=1
# CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH=1

147
bootloader/mcuboot/boot/espressif/port/esp32s2/ld/bootloader.ld Normal file
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/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Simplified memory map for the bootloader.
*
* The main purpose is to make sure the bootloader can load into main memory
* without overwriting itself.
*/
MEMORY
{
iram_seg (RWX) : org = 0x40047000, len = 0x9000
iram_loader_seg (RWX) : org = 0x40050000, len = 0x6000
dram_seg (RW) : org = 0x3FFE6000, len = 0x9000
}
/* Default entry point: */
ENTRY(main);
SECTIONS
{
.iram_loader.text :
{
. = ALIGN (16);
_loader_text_start = ABSOLUTE(.);
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
*libhal.a:*.*(.literal .text .literal.* .text.*)
*esp_mcuboot.*(.literal .text .literal.* .text.*)
*esp_loader.*(.literal .text .literal.* .text.*)
*main.*(.literal .text .literal.* .text.*)
*(.fini.literal)
*(.fini)
*(.gnu.version)
_loader_text_end = ABSOLUTE(.);
} > iram_loader_seg
.iram.text :
{
. = ALIGN (16);
*(.entry.text)
*(.init.literal)
*(.init)
} > iram_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
. = ALIGN (8);
_dram_start = ABSOLUTE(.);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
} >dram_seg
.dram0.data :
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
*(.jcr)
_data_end = ABSOLUTE(.);
} >dram_seg
.dram0.rodata :
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
*(.eh_frame)
. = (. + 3) & ~ 3;
/* C++ constructor and destructor tables, properly ordered: */
__init_array_start = ABSOLUTE(.);
KEEP (*crtbegin.*(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__init_array_end = ABSOLUTE(.);
KEEP (*crtbegin.*(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
_rodata_end = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
_dram_end = ABSOLUTE(.);
} >dram_seg
.iram.text :
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram .iram.*) /* catch stray IRAM_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} > iram_seg
}

191
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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdio.h>
#include <string.h>
#include <bootutil/bootutil_log.h>
#include <esp_rom_uart.h>
#include <esp_rom_gpio.h>
#include <esp_rom_sys.h>
#include <esp_rom_caps.h>
#include <soc/uart_periph.h>
#include <soc/gpio_struct.h>
#include <soc/io_mux_reg.h>
#include <soc/rtc.h>
#include <hal/gpio_types.h>
#include <hal/gpio_ll.h>
#include <hal/uart_ll.h>
#include <hal/clk_gate_ll.h>
#include <hal/gpio_hal.h>
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT
#define SERIAL_BOOT_GPIO_DETECT CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT
#else
#define SERIAL_BOOT_GPIO_DETECT GPIO_NUM_5
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL
#define SERIAL_BOOT_GPIO_DETECT_VAL CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL
#else
#define SERIAL_BOOT_GPIO_DETECT_VAL 1
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S
#define SERIAL_BOOT_DETECT_DELAY_S CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S
#else
#define SERIAL_BOOT_DETECT_DELAY_S 5
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE
#define SERIAL_BOOT_GPIO_INPUT_TYPE CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE
#else
// pull-down
#define SERIAL_BOOT_GPIO_INPUT_TYPE 0
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_UART_NUM
#define SERIAL_BOOT_UART_NUM CONFIG_ESP_SERIAL_BOOT_UART_NUM
#else
#define SERIAL_BOOT_UART_NUM ESP_ROM_UART_1
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_RX
#define SERIAL_BOOT_GPIO_RX CONFIG_ESP_SERIAL_BOOT_GPIO_RX
#else
#define SERIAL_BOOT_GPIO_RX GPIO_NUM_18
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_TX
#define SERIAL_BOOT_GPIO_TX CONFIG_ESP_SERIAL_BOOT_GPIO_TX
#else
#define SERIAL_BOOT_GPIO_TX GPIO_NUM_17
#endif
static uart_dev_t *serial_boot_uart_dev = (SERIAL_BOOT_UART_NUM == 0) ?
&UART0 :
&UART1;
void console_write(const char *str, int cnt)
{
uint32_t tx_len;
uint32_t write_len;
do {
tx_len = uart_ll_get_txfifo_len(serial_boot_uart_dev);
if (tx_len > 0) {
write_len = tx_len < cnt ? tx_len : cnt;
uart_ll_write_txfifo(serial_boot_uart_dev, (const uint8_t *)str, write_len);
cnt -= write_len;
}
MCUBOOT_WATCHDOG_FEED();
esp_rom_delay_us(1000);
} while (cnt > 0);
}
int console_read(char *str, int cnt, int *newline)
{
uint32_t len = 0;
uint32_t read_len = 0;
bool stop = false;
do {
len = uart_ll_get_rxfifo_len(serial_boot_uart_dev);
if (len > 0) {
for (uint32_t i = 0; i < len; i++) {
/* Read the character from the RX FIFO */
uart_ll_read_rxfifo(serial_boot_uart_dev, (uint8_t *)&str[read_len], 1);
read_len++;
if (read_len == cnt - 1|| str[read_len - 1] == '\n') {
stop = true;
break;
}
}
}
MCUBOOT_WATCHDOG_FEED();
esp_rom_delay_us(1000);
} while (!stop);
*newline = (str[read_len - 1] == '\n') ? 1 : 0;
return read_len;
}
int boot_console_init(void)
{
BOOT_LOG_INF("Initializing serial boot pins");
/* Enable GPIO for UART RX */
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_RX);
esp_rom_gpio_connect_in_signal(SERIAL_BOOT_GPIO_RX,
UART_PERIPH_SIGNAL(SERIAL_BOOT_UART_NUM, SOC_UART_RX_PIN_IDX),
0);
gpio_ll_input_enable(&GPIO, SERIAL_BOOT_GPIO_RX);
esp_rom_gpio_pad_pullup_only(SERIAL_BOOT_GPIO_RX);
/* Enable GPIO for UART TX */
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_TX);
esp_rom_gpio_connect_out_signal(SERIAL_BOOT_GPIO_TX,
UART_PERIPH_SIGNAL(SERIAL_BOOT_UART_NUM, SOC_UART_TX_PIN_IDX),
0, 0);
gpio_ll_output_enable(&GPIO, SERIAL_BOOT_GPIO_TX);
uart_ll_set_sclk(serial_boot_uart_dev, UART_SCLK_APB);
uart_ll_set_mode_normal(serial_boot_uart_dev);
uart_ll_set_baudrate(serial_boot_uart_dev, 115200, UART_SCLK_APB);
uart_ll_set_stop_bits(serial_boot_uart_dev, 1u);
uart_ll_set_parity(serial_boot_uart_dev, UART_PARITY_DISABLE);
uart_ll_set_rx_tout(serial_boot_uart_dev, 16);
uart_ll_set_data_bit_num(serial_boot_uart_dev, UART_DATA_8_BITS);
uart_ll_set_tx_idle_num(serial_boot_uart_dev, 0);
uart_ll_set_hw_flow_ctrl(serial_boot_uart_dev, UART_HW_FLOWCTRL_DISABLE, 100);
periph_ll_enable_clk_clear_rst(PERIPH_UART0_MODULE + SERIAL_BOOT_UART_NUM);
uart_ll_txfifo_rst(serial_boot_uart_dev);
uart_ll_rxfifo_rst(serial_boot_uart_dev);
esp_rom_delay_us(50000);
return 0;
}
bool boot_serial_detect_pin(void)
{
bool detected = false;
int pin_value = 0;
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_DETECT);
gpio_ll_input_enable(&GPIO, SERIAL_BOOT_GPIO_DETECT);
switch (SERIAL_BOOT_GPIO_INPUT_TYPE) {
// Pull-down
case 0:
gpio_ll_pulldown_en(&GPIO, SERIAL_BOOT_GPIO_DETECT);
break;
// Pull-up
case 1:
gpio_ll_pullup_en(&GPIO, SERIAL_BOOT_GPIO_DETECT);
break;
}
esp_rom_delay_us(50000);
pin_value = gpio_ll_get_level(&GPIO, SERIAL_BOOT_GPIO_DETECT);
detected = (pin_value == SERIAL_BOOT_GPIO_DETECT_VAL);
esp_rom_delay_us(50000);
if (detected) {
if (SERIAL_BOOT_DETECT_DELAY_S > 0) {
/* The delay time is an approximation */
for (int i = 0; i < (SERIAL_BOOT_DETECT_DELAY_S * 100); i++) {
esp_rom_delay_us(10000);
pin_value = gpio_ll_get_level(&GPIO, SERIAL_BOOT_GPIO_DETECT);
detected = (pin_value == SERIAL_BOOT_GPIO_DETECT_VAL);
if (!detected) {
break;
}
}
}
}
return detected;
}

38
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# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
#
# SPDX-License-Identifier: Apache-2.0
CONFIG_ESP_FLASH_SIZE=4MB
CONFIG_ESP_BOOTLOADER_SIZE=0xF000
CONFIG_ESP_BOOTLOADER_OFFSET=0x0000
CONFIG_ESP_MCUBOOT_WDT_ENABLE=y
# Example of values to be used when multi image is enabled
# Notice that the OS layer and update agent must be aware
# of these regions
CONFIG_ESP_APPLICATION_SIZE=0x80000
CONFIG_ESP_IMAGE0_PRIMARY_START_ADDRESS=0x10000
CONFIG_ESP_IMAGE0_SECONDARY_START_ADDRESS=0x90000
CONFIG_ESP_IMAGE1_PRIMARY_START_ADDRESS=0x110000
CONFIG_ESP_IMAGE1_SECONDARY_START_ADDRESS=0x190000
CONFIG_ESP_SCRATCH_OFFSET=0x210000
CONFIG_ESP_SCRATCH_SIZE=0x40000
# Use UART0 for console printing (use either UART or USB alone)
CONFIG_ESP_CONSOLE_UART=y
CONFIG_ESP_CONSOLE_UART_NUM=0
# Configures alternative UART port for console printing
# (UART_NUM=0 must not be changed)
# CONFIG_ESP_CONSOLE_UART_CUSTOM=y
# CONFIG_ESP_CONSOLE_UART_TX_GPIO=17
# CONFIG_ESP_CONSOLE_UART_RX_GPIO=18
# Use USB JTAG Serial for console printing
# CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y
# Enables multi image, if it is not defined, it is assumed
# only one updatable image
# CONFIG_ESP_IMAGE_NUMBER=2
# Enables multi image boot on independent processors
# (main host OS is not responsible for booting the second image)
# Use only with CONFIG_ESP_IMAGE_NUMBER=2
# CONFIG_ESP_MULTI_PROCESSOR_BOOT=y

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bootloader/mcuboot/boot/espressif/port/esp32s3/bootloader.conf Normal file
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# SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
#
# SPDX-License-Identifier: Apache-2.0
CONFIG_ESP_FLASH_SIZE=4MB
CONFIG_ESP_BOOTLOADER_SIZE=0xF000
CONFIG_ESP_BOOTLOADER_OFFSET=0x0000
CONFIG_ESP_IMAGE0_PRIMARY_START_ADDRESS=0x10000
CONFIG_ESP_APPLICATION_SIZE=0x100000
CONFIG_ESP_IMAGE0_SECONDARY_START_ADDRESS=0x110000
CONFIG_ESP_MCUBOOT_WDT_ENABLE=y
CONFIG_ESP_SCRATCH_OFFSET=0x210000
CONFIG_ESP_SCRATCH_SIZE=0x40000
# When enabled, prevents updating image to an older version
# CONFIG_ESP_DOWNGRADE_PREVENTION=y
# This option makes downgrade prevention rely also on security
# counter (defined using imgtool) instead of only image version
# CONFIG_ESP_DOWNGRADE_PREVENTION_SECURITY_COUNTER=y
# Enables multi image, if it is not defined, it is assumed
# only one updatable image
# CONFIG_ESP_IMAGE_NUMBER=2
# Enables multi image boot on independent processors
# (main host OS is not responsible for booting the second image)
# Use only with CONFIG_ESP_IMAGE_NUMBER=2
# CONFIG_ESP_MULTI_PROCESSOR_BOOT=y
# Example of values to be used when multi image is enabled
# Notice that the OS layer and update agent must be aware
# of these regions
# CONFIG_ESP_APPLICATION_SIZE=0x80000
# CONFIG_ESP_IMAGE0_PRIMARY_START_ADDRESS=0x10000
# CONFIG_ESP_IMAGE0_SECONDARY_START_ADDRESS=0x90000
# CONFIG_ESP_IMAGE1_PRIMARY_START_ADDRESS=0x110000
# CONFIG_ESP_IMAGE1_SECONDARY_START_ADDRESS=0x190000
# CONFIG_ESP_SCRATCH_OFFSET=0x210000
# CONFIG_ESP_SCRATCH_SIZE=0x40000
# Enables the MCUboot Serial Recovery, that allows the use of
# MCUMGR to upload a firmware through the serial port
# CONFIG_ESP_MCUBOOT_SERIAL=y
# Use Serial through USB JTAG Serial port for Serial Recovery
# CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG=y
# Use sector erasing (recommended) instead of entire image size
# erasing when uploading through Serial Recovery
# CONFIG_ESP_MCUBOOT_ERASE_PROGRESSIVELY=y
# GPIO used to boot on Serial Recovery
# CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT=5
# GPIO input type (0 for Pull-down, 1 for Pull-up)
# CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE=0
# GPIO signal value
# CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL=1
# Delay time for identify the GPIO signal
# CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S=5
# UART port used for serial communication (not needed when using USB)
# CONFIG_ESP_SERIAL_BOOT_UART_NUM=1
# GPIO for Serial RX signal
# CONFIG_ESP_SERIAL_BOOT_GPIO_RX=18
# GPIO for Serial TX signal
# CONFIG_ESP_SERIAL_BOOT_GPIO_TX=17
# Use UART0 for console printing (use either UART or USB alone)
CONFIG_ESP_CONSOLE_UART=y
CONFIG_ESP_CONSOLE_UART_NUM=0
# Configures alternative UART port for console printing
# (UART_NUM=0 must not be changed)
# CONFIG_ESP_CONSOLE_UART_CUSTOM=y
# CONFIG_ESP_CONSOLE_UART_TX_GPIO=17
# CONFIG_ESP_CONSOLE_UART_RX_GPIO=18
# Use USB JTAG Serial for console printing
# CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y
# CONFIG_ESP_SIGN_EC256=y
# CONFIG_ESP_SIGN_ED25519=n
# CONFIG_ESP_SIGN_RSA=n
# CONFIG_ESP_SIGN_RSA_LEN=2048
# Use Tinycrypt lib for EC256 or ED25519 signing
# CONFIG_ESP_USE_TINYCRYPT=y
# Use Mbed TLS lib for RSA image signing
# CONFIG_ESP_USE_MBEDTLS=n
# It is strongly recommended to generate a new signing key
# using imgtool instead of use the existent sample
# CONFIG_ESP_SIGN_KEY_FILE=root-ec-p256.pem
# Hardware Secure Boot related options
# CONFIG_SECURE_SIGNED_ON_BOOT=1
# CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME=1
# CONFIG_SECURE_BOOT=1
# CONFIG_SECURE_BOOT_V2_ENABLED=1
# CONFIG_SECURE_BOOT_SUPPORTS_RSA=1
# Hardware Flash Encryption related options
# CONFIG_SECURE_FLASH_ENC_ENABLED=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC=1
# CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE=1
# CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT=1
# CONFIG_SECURE_BOOT_ALLOW_JTAG=1
# CONFIG_SECURE_BOOT_ALLOW_ROM_BASIC=1
# Options for enabling eFuse emulation in Flash
# CONFIG_EFUSE_VIRTUAL=1
# CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH=1

147
bootloader/mcuboot/boot/espressif/port/esp32s3/ld/bootloader.ld Normal file
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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Simplified memory map for the bootloader.
*
* The main purpose is to make sure the bootloader can load into main memory
* without overwriting itself.
*/
MEMORY
{
iram_seg (RWX) : org = 0x403B0000, len = 0xA000
iram_loader_seg (RWX) : org = 0x403BA000, len = 0x6000
dram_seg (RW) : org = 0x3FCD0000, len = 0x9A00
}
/* Default entry point: */
ENTRY(main);
SECTIONS
{
.iram_loader.text :
{
. = ALIGN (16);
_loader_text_start = ABSOLUTE(.);
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
*libhal.a:*.*(.literal .text .literal.* .text.*)
*esp_mcuboot.*(.literal .text .literal.* .text.*)
*esp_loader.*(.literal .text .literal.* .text.*)
*main.*(.literal .text .literal.* .text.*)
*(.fini.literal)
*(.fini)
*(.gnu.version)
_loader_text_end = ABSOLUTE(.);
} > iram_loader_seg
.iram.text :
{
. = ALIGN (16);
*(.entry.text)
*(.init.literal)
*(.init)
} > iram_seg
/* Shared RAM */
.dram0.bss (NOLOAD) :
{
. = ALIGN (8);
_dram_start = ABSOLUTE(.);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
} >dram_seg
.dram0.data :
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
*(.jcr)
_data_end = ABSOLUTE(.);
} >dram_seg
.dram0.rodata :
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
*(.eh_frame)
. = (. + 3) & ~ 3;
/* C++ constructor and destructor tables, properly ordered: */
__init_array_start = ABSOLUTE(.);
KEEP (*crtbegin.*(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__init_array_end = ABSOLUTE(.);
KEEP (*crtbegin.*(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
_rodata_end = ABSOLUTE(.);
/* Literals are also RO data. */
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
. = ALIGN(4);
_dram_end = ABSOLUTE(.);
} >dram_seg
.iram.text :
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.iram .iram.*) /* catch stray IRAM_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} > iram_seg
}

228
bootloader/mcuboot/boot/espressif/port/esp32s3/serial_adapter.c Normal file
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/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdio.h>
#include <string.h>
#include <bootutil/bootutil_log.h>
#include <esp_rom_uart.h>
#include <esp_rom_gpio.h>
#include <esp_rom_sys.h>
#include <esp_rom_caps.h>
#include <soc/uart_periph.h>
#include <soc/gpio_struct.h>
#include <soc/io_mux_reg.h>
#include <soc/rtc.h>
#include <hal/gpio_types.h>
#include <hal/gpio_ll.h>
#include <hal/uart_ll.h>
#include <hal/clk_gate_ll.h>
#include <hal/gpio_hal.h>
#include <hal/usb_serial_jtag_ll.h>
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT
#define SERIAL_BOOT_GPIO_DETECT CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT
#else
#define SERIAL_BOOT_GPIO_DETECT GPIO_NUM_5
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL
#define SERIAL_BOOT_GPIO_DETECT_VAL CONFIG_ESP_SERIAL_BOOT_GPIO_DETECT_VAL
#else
#define SERIAL_BOOT_GPIO_DETECT_VAL 1
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S
#define SERIAL_BOOT_DETECT_DELAY_S CONFIG_ESP_SERIAL_BOOT_DETECT_DELAY_S
#else
#define SERIAL_BOOT_DETECT_DELAY_S 5
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE
#define SERIAL_BOOT_GPIO_INPUT_TYPE CONFIG_ESP_SERIAL_BOOT_GPIO_INPUT_TYPE
#else
// pull-down
#define SERIAL_BOOT_GPIO_INPUT_TYPE 0
#endif
#ifndef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
#ifdef CONFIG_ESP_SERIAL_BOOT_UART_NUM
#define SERIAL_BOOT_UART_NUM CONFIG_ESP_SERIAL_BOOT_UART_NUM
#else
#define SERIAL_BOOT_UART_NUM ESP_ROM_UART_1
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_RX
#define SERIAL_BOOT_GPIO_RX CONFIG_ESP_SERIAL_BOOT_GPIO_RX
#else
#define SERIAL_BOOT_GPIO_RX GPIO_NUM_18
#endif
#ifdef CONFIG_ESP_SERIAL_BOOT_GPIO_TX
#define SERIAL_BOOT_GPIO_TX CONFIG_ESP_SERIAL_BOOT_GPIO_TX
#else
#define SERIAL_BOOT_GPIO_TX GPIO_NUM_17
#endif
static uart_dev_t *serial_boot_uart_dev = (SERIAL_BOOT_UART_NUM == 0) ?
&UART0 :
&UART1;
#endif
void console_write(const char *str, int cnt)
{
#ifdef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
usb_serial_jtag_ll_txfifo_flush();
while (!usb_serial_jtag_ll_txfifo_writable()) {
MCUBOOT_WATCHDOG_FEED();
}
usb_serial_jtag_ll_write_txfifo((const uint8_t *)str, cnt);
usb_serial_jtag_ll_txfifo_flush();
#else
uint32_t tx_len;
uint32_t write_len;
do {
tx_len = uart_ll_get_txfifo_len(serial_boot_uart_dev);
if (tx_len > 0) {
write_len = tx_len < cnt ? tx_len : cnt;
uart_ll_write_txfifo(serial_boot_uart_dev, (const uint8_t *)str, write_len);
cnt -= write_len;
}
MCUBOOT_WATCHDOG_FEED();
esp_rom_delay_us(1000);
} while (cnt > 0);
#endif
}
int console_read(char *str, int cnt, int *newline)
{
#ifdef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
uint32_t read_len = 0;
esp_rom_delay_us(1000);
do {
if (usb_serial_jtag_ll_rxfifo_data_available()) {
usb_serial_jtag_ll_read_rxfifo((uint8_t *)&str[read_len], 1);
read_len++;
}
MCUBOOT_WATCHDOG_FEED();
esp_rom_delay_us(1000);
} while (!(read_len == cnt || str[read_len - 1] == '\n'));
*newline = (str[read_len - 1] == '\n') ? 1 : 0;
return read_len;
#else
uint32_t len = 0;
uint32_t read_len = 0;
bool stop = false;
do {
len = uart_ll_get_rxfifo_len(serial_boot_uart_dev);
if (len > 0) {
for (uint32_t i = 0; i < len; i++) {
/* Read the character from the RX FIFO */
uart_ll_read_rxfifo(serial_boot_uart_dev, (uint8_t *)&str[read_len], 1);
read_len++;
if (read_len == cnt - 1|| str[read_len - 1] == '\n') {
stop = true;
break;
}
}
}
MCUBOOT_WATCHDOG_FEED();
esp_rom_delay_us(1000);
} while (!stop);
*newline = (str[read_len - 1] == '\n') ? 1 : 0;
return read_len;
#endif
}
int boot_console_init(void)
{
BOOT_LOG_INF("Initializing serial boot pins");
#ifdef CONFIG_ESP_MCUBOOT_SERIAL_USB_SERIAL_JTAG
usb_serial_jtag_ll_txfifo_flush();
esp_rom_uart_tx_wait_idle(0);
#else
/* Enable GPIO for UART RX */
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_RX);
esp_rom_gpio_connect_in_signal(SERIAL_BOOT_GPIO_RX,
UART_PERIPH_SIGNAL(SERIAL_BOOT_UART_NUM, SOC_UART_RX_PIN_IDX),
0);
gpio_ll_input_enable(&GPIO, SERIAL_BOOT_GPIO_RX);
esp_rom_gpio_pad_pullup_only(SERIAL_BOOT_GPIO_RX);
/* Enable GPIO for UART TX */
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_TX);
esp_rom_gpio_connect_out_signal(SERIAL_BOOT_GPIO_TX,
UART_PERIPH_SIGNAL(SERIAL_BOOT_UART_NUM, SOC_UART_TX_PIN_IDX),
0, 0);
gpio_ll_output_enable(&GPIO, SERIAL_BOOT_GPIO_TX);
uart_ll_set_sclk(serial_boot_uart_dev, UART_SCLK_APB);
uart_ll_set_mode_normal(serial_boot_uart_dev);
uart_ll_set_baudrate(serial_boot_uart_dev, 115200, UART_SCLK_APB);
uart_ll_set_stop_bits(serial_boot_uart_dev, 1u);
uart_ll_set_parity(serial_boot_uart_dev, UART_PARITY_DISABLE);
uart_ll_set_rx_tout(serial_boot_uart_dev, 16);
uart_ll_set_data_bit_num(serial_boot_uart_dev, UART_DATA_8_BITS);
uart_ll_set_tx_idle_num(serial_boot_uart_dev, 0);
uart_ll_set_hw_flow_ctrl(serial_boot_uart_dev, UART_HW_FLOWCTRL_DISABLE, 100);
periph_ll_enable_clk_clear_rst(PERIPH_UART0_MODULE + SERIAL_BOOT_UART_NUM);
uart_ll_txfifo_rst(serial_boot_uart_dev);
uart_ll_rxfifo_rst(serial_boot_uart_dev);
esp_rom_delay_us(50000);
#endif
return 0;
}
bool boot_serial_detect_pin(void)
{
bool detected = false;
int pin_value = 0;
esp_rom_gpio_pad_select_gpio(SERIAL_BOOT_GPIO_DETECT);
gpio_ll_input_enable(&GPIO, SERIAL_BOOT_GPIO_DETECT);
switch (SERIAL_BOOT_GPIO_INPUT_TYPE) {
// Pull-down
case 0:
gpio_ll_pulldown_en(&GPIO, SERIAL_BOOT_GPIO_DETECT);
break;
// Pull-up
case 1:
gpio_ll_pullup_en(&GPIO, SERIAL_BOOT_GPIO_DETECT);
break;
}
esp_rom_delay_us(50000);
pin_value = gpio_ll_get_level(&GPIO, SERIAL_BOOT_GPIO_DETECT);
detected = (pin_value == SERIAL_BOOT_GPIO_DETECT_VAL);
esp_rom_delay_us(50000);
if (detected) {
if (SERIAL_BOOT_DETECT_DELAY_S > 0) {
/* The delay time is an approximation */
for (int i = 0; i < (SERIAL_BOOT_DETECT_DELAY_S * 100); i++) {
esp_rom_delay_us(10000);
pin_value = gpio_ll_get_level(&GPIO, SERIAL_BOOT_GPIO_DETECT);
detected = (pin_value == SERIAL_BOOT_GPIO_DETECT_VAL);
if (!detected) {
break;
}
}
}
}
return detected;
}

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/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <bootutil/bootutil_log.h>
#include <bootutil/fault_injection_hardening.h>
#include "bootloader_memory_utils.h"
#include "bootloader_flash_priv.h"
#include "esp_flash_encrypt.h"
#include "rom/uart.h"
#include "esp_mcuboot_image.h"
#include "esp_loader.h"
#include "flash_map_backend/flash_map_backend.h"
#ifdef CONFIG_ESP_MULTI_PROCESSOR_BOOT
#include "app_cpu_start.h"
#endif
static int load_segment(const struct flash_area *fap, uint32_t data_addr, uint32_t data_len, uint32_t load_addr)
{
const uint32_t *data = (const uint32_t *)bootloader_mmap((fap->fa_off + data_addr), data_len);
if (!data) {
BOOT_LOG_ERR("%s: Bootloader mmap failed", __func__);
return -1;
}
memcpy((void *)load_addr, data, data_len);
bootloader_munmap(data);
return 0;
}
void esp_app_image_load(int image_index, int slot, unsigned int hdr_offset, unsigned int *entry_addr)
{
const struct flash_area *fap;
int area_id;
int rc;
area_id = flash_area_id_from_multi_image_slot(image_index, slot);
rc = flash_area_open(area_id, &fap);
if (rc != 0) {
BOOT_LOG_ERR("%s: flash_area_open failed with %d", __func__, rc);
}
BOOT_LOG_INF("Loading image %d - slot %d from flash, area id: %d", image_index, slot, area_id);
const uint32_t *data = (const uint32_t *)bootloader_mmap((fap->fa_off + hdr_offset), sizeof(esp_image_load_header_t));
esp_image_load_header_t load_header = {0};
memcpy((void *)&load_header, data, sizeof(esp_image_load_header_t));
bootloader_munmap(data);
if (load_header.header_magic != ESP_LOAD_HEADER_MAGIC) {
BOOT_LOG_ERR("Load header magic verification failed. Aborting");
FIH_PANIC;
}
if (!esp_ptr_in_iram((void *)load_header.iram_dest_addr) || !esp_ptr_in_iram((void *)(load_header.iram_dest_addr + load_header.iram_size))) {
BOOT_LOG_ERR("IRAM region in load header is not valid. Aborting");
FIH_PANIC;
}
if (!esp_ptr_in_dram((void *)load_header.dram_dest_addr) || !esp_ptr_in_dram((void *)(load_header.dram_dest_addr + load_header.dram_size))) {
BOOT_LOG_ERR("DRAM region in load header is not valid. Aborting");
FIH_PANIC;
}
if (!esp_ptr_in_iram((void *)load_header.entry_addr)) {
BOOT_LOG_ERR("Application entry point (0x%x) is not in IRAM. Aborting", load_header.entry_addr);
FIH_PANIC;
}
BOOT_LOG_INF("DRAM segment: start=0x%x, size=0x%x, vaddr=0x%x", fap->fa_off + load_header.dram_flash_offset, load_header.dram_size, load_header.dram_dest_addr);
load_segment(fap, load_header.dram_flash_offset, load_header.dram_size, load_header.dram_dest_addr);
BOOT_LOG_INF("IRAM segment: start=0x%x, size=0x%x, vaddr=0x%x", fap->fa_off + load_header.iram_flash_offset, load_header.iram_size, load_header.iram_dest_addr);
load_segment(fap, load_header.iram_flash_offset, load_header.iram_size, load_header.iram_dest_addr);
BOOT_LOG_INF("start=0x%x", load_header.entry_addr);
uart_tx_wait_idle(0);
assert(entry_addr != NULL);
*entry_addr = load_header.entry_addr;
}
void start_cpu0_image(int image_index, int slot, unsigned int hdr_offset)
{
unsigned int entry_addr;
esp_app_image_load(image_index, slot, hdr_offset, &entry_addr);
((void (*)(void))entry_addr)(); /* Call to application entry address should not return */
FIH_PANIC; /* It should not get here */
}
#ifdef CONFIG_ESP_MULTI_PROCESSOR_BOOT
void start_cpu1_image(int image_index, int slot, unsigned int hdr_offset)
{
unsigned int entry_addr;
esp_app_image_load(image_index, slot, hdr_offset, &entry_addr);
appcpu_start(entry_addr);
}
#endif

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/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include <stdlib.h>
#include <string.h>
#include <bootutil/bootutil.h>
#include <bootutil/bootutil_log.h>
#include "sdkconfig.h"
#include "esp_err.h"
#include "bootloader_flash_priv.h"
#include "esp_flash_encrypt.h"
#include "flash_map_backend/flash_map_backend.h"
#include "sysflash/sysflash.h"
#ifndef ARRAY_SIZE
# define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
#endif
#ifndef MIN
# define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#ifndef ALIGN_UP
# define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
#endif
#ifndef ALIGN_DOWN
# define ALIGN_DOWN(num, align) ((num) & ~((align) - 1))
#endif
#ifndef ALIGN_OFFSET
# define ALIGN_OFFSET(num, align) ((num) & ((align) - 1))
#endif
#ifndef IS_ALIGNED
# define IS_ALIGNED(num, align) (ALIGN_OFFSET((num), (align)) == 0)
#endif
#define FLASH_BUFFER_SIZE 256 /* SPI Flash block size */
_Static_assert(IS_ALIGNED(FLASH_BUFFER_SIZE, 4), "Buffer size for SPI Flash operations must be 4-byte aligned.");
#define BOOTLOADER_START_ADDRESS CONFIG_BOOTLOADER_OFFSET_IN_FLASH
#define BOOTLOADER_SIZE CONFIG_ESP_BOOTLOADER_SIZE
#define IMAGE0_PRIMARY_START_ADDRESS CONFIG_ESP_IMAGE0_PRIMARY_START_ADDRESS
#define IMAGE0_SECONDARY_START_ADDRESS CONFIG_ESP_IMAGE0_SECONDARY_START_ADDRESS
#define SCRATCH_OFFSET CONFIG_ESP_SCRATCH_OFFSET
#if (MCUBOOT_IMAGE_NUMBER == 2)
#define IMAGE1_PRIMARY_START_ADDRESS CONFIG_ESP_IMAGE1_PRIMARY_START_ADDRESS
#define IMAGE1_SECONDARY_START_ADDRESS CONFIG_ESP_IMAGE1_SECONDARY_START_ADDRESS
#endif
#define APPLICATION_SIZE CONFIG_ESP_APPLICATION_SIZE
#define SCRATCH_SIZE CONFIG_ESP_SCRATCH_SIZE
extern int ets_printf(const char *fmt, ...);
static const struct flash_area bootloader = {
.fa_id = FLASH_AREA_BOOTLOADER,
.fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
.fa_off = BOOTLOADER_START_ADDRESS,
.fa_size = BOOTLOADER_SIZE,
};
static const struct flash_area primary_img0 = {
.fa_id = FLASH_AREA_IMAGE_PRIMARY(0),
.fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
.fa_off = IMAGE0_PRIMARY_START_ADDRESS,
.fa_size = APPLICATION_SIZE,
};
static const struct flash_area secondary_img0 = {
.fa_id = FLASH_AREA_IMAGE_SECONDARY(0),
.fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
.fa_off = IMAGE0_SECONDARY_START_ADDRESS,
.fa_size = APPLICATION_SIZE,
};
#if (MCUBOOT_IMAGE_NUMBER == 2)
static const struct flash_area primary_img1 = {
.fa_id = FLASH_AREA_IMAGE_PRIMARY(1),
.fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
.fa_off = IMAGE1_PRIMARY_START_ADDRESS,
.fa_size = APPLICATION_SIZE,
};
static const struct flash_area secondary_img1 = {
.fa_id = FLASH_AREA_IMAGE_SECONDARY(1),
.fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
.fa_off = IMAGE1_SECONDARY_START_ADDRESS,
.fa_size = APPLICATION_SIZE,
};
#endif
static const struct flash_area scratch_img0 = {
.fa_id = FLASH_AREA_IMAGE_SCRATCH,
.fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
.fa_off = SCRATCH_OFFSET,
.fa_size = SCRATCH_SIZE,
};
static const struct flash_area *s_flash_areas[] = {
&bootloader,
&primary_img0,
&secondary_img0,
#if (MCUBOOT_IMAGE_NUMBER == 2)
&primary_img1,
&secondary_img1,
#endif
&scratch_img0,
};
static const struct flash_area *prv_lookup_flash_area(uint8_t id) {
for (size_t i = 0; i < ARRAY_SIZE(s_flash_areas); i++) {
const struct flash_area *area = s_flash_areas[i];
if (id == area->fa_id) {
return area;
}
}
return NULL;
}
int flash_area_open(uint8_t id, const struct flash_area **area_outp)
{
BOOT_LOG_DBG("%s: ID=%d", __func__, (int)id);
const struct flash_area *area = prv_lookup_flash_area(id);
*area_outp = area;
return area != NULL ? 0 : -1;
}
void flash_area_close(const struct flash_area *area)
{
}
static bool aligned_flash_read(uintptr_t addr, void *dest, size_t size)
{
if (IS_ALIGNED(addr, 4) && IS_ALIGNED((uintptr_t)dest, 4) && IS_ALIGNED(size, 4)) {
/* A single read operation is enough when when all parameters are aligned */
return bootloader_flash_read(addr, dest, size, true) == ESP_OK;
}
const uint32_t aligned_addr = ALIGN_DOWN(addr, 4);
const uint32_t addr_offset = ALIGN_OFFSET(addr, 4);
uint32_t bytes_remaining = size;
uint8_t read_data[FLASH_BUFFER_SIZE] = {0};
/* Align the read address to 4-byte boundary and ensure read size is a multiple of 4 bytes */
uint32_t bytes = MIN(bytes_remaining + addr_offset, sizeof(read_data));
if (bootloader_flash_read(aligned_addr, read_data, ALIGN_UP(bytes, 4), true) != ESP_OK) {
return false;
}
/* Skip non-useful data which may have been read for adjusting the alignment */
uint32_t bytes_read = bytes - addr_offset;
memcpy(dest, &read_data[addr_offset], bytes_read);
bytes_remaining -= bytes_read;
/* Read remaining data from Flash in case requested size is greater than buffer size */
uint32_t offset = bytes;
while (bytes_remaining != 0) {
bytes = MIN(bytes_remaining, sizeof(read_data));
if (bootloader_flash_read(aligned_addr + offset, read_data, ALIGN_UP(bytes, 4), true) != ESP_OK) {
return false;
}
memcpy(&((uint8_t *)dest)[bytes_read], read_data, bytes);
offset += bytes;
bytes_read += bytes;
bytes_remaining -= bytes;
}
return true;
}
int flash_area_read(const struct flash_area *fa, uint32_t off, void *dst,
uint32_t len)
{
if (fa->fa_device_id != FLASH_DEVICE_INTERNAL_FLASH) {
return -1;
}
const uint32_t end_offset = off + len;
if (end_offset > fa->fa_size) {
BOOT_LOG_ERR("%s: Out of Bounds (0x%x vs 0x%x)", __func__, end_offset, fa->fa_size);
return -1;
}
bool success = aligned_flash_read(fa->fa_off + off, dst, len);
if (!success) {
BOOT_LOG_ERR("%s: Flash read failed", __func__);
return -1;
}
return 0;
}
static bool aligned_flash_write(size_t dest_addr, const void *src, size_t size)
{
#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED
bool flash_encryption_enabled = esp_flash_encryption_enabled();
#else
bool flash_encryption_enabled = false;
#endif
if (IS_ALIGNED(dest_addr, 4) && IS_ALIGNED((uintptr_t)src, 4) && IS_ALIGNED(size, 4)) {
/* A single write operation is enough when all parameters are aligned */
return bootloader_flash_write(dest_addr, (void *)src, size, flash_encryption_enabled) == ESP_OK;
}
const uint32_t aligned_addr = ALIGN_DOWN(dest_addr, 4);
const uint32_t addr_offset = ALIGN_OFFSET(dest_addr, 4);
uint32_t bytes_remaining = size;
uint8_t write_data[FLASH_BUFFER_SIZE] = {0};
/* Perform a read operation considering an offset not aligned to 4-byte boundary */
uint32_t bytes = MIN(bytes_remaining + addr_offset, sizeof(write_data));
if (bootloader_flash_read(aligned_addr, write_data, ALIGN_UP(bytes, 4), true) != ESP_OK) {
return false;
}
uint32_t bytes_written = bytes - addr_offset;
memcpy(&write_data[addr_offset], src, bytes_written);
if (bootloader_flash_write(aligned_addr, write_data, ALIGN_UP(bytes, 4), flash_encryption_enabled) != ESP_OK) {
return false;
}
bytes_remaining -= bytes_written;
/* Write remaining data to Flash if any */
uint32_t offset = bytes;
while (bytes_remaining != 0) {
bytes = MIN(bytes_remaining, sizeof(write_data));
if (bootloader_flash_read(aligned_addr + offset, write_data, ALIGN_UP(bytes, 4), true) != ESP_OK) {
return false;
}
memcpy(write_data, &((uint8_t *)src)[bytes_written], bytes);
if (bootloader_flash_write(aligned_addr + offset, write_data, ALIGN_UP(bytes, 4), flash_encryption_enabled) != ESP_OK) {
return false;
}
offset += bytes;
bytes_written += bytes;
bytes_remaining -= bytes;
}
return true;
}
int flash_area_write(const struct flash_area *fa, uint32_t off, const void *src,
uint32_t len)
{
if (fa->fa_device_id != FLASH_DEVICE_INTERNAL_FLASH) {
return -1;
}
const uint32_t end_offset = off + len;
if (end_offset > fa->fa_size) {
BOOT_LOG_ERR("%s: Out of Bounds (0x%x vs 0x%x)", __func__, end_offset, fa->fa_size);
return -1;
}
const uint32_t start_addr = fa->fa_off + off;
BOOT_LOG_DBG("%s: Addr: 0x%08x Length: %d", __func__, (int)start_addr, (int)len);
bool success = aligned_flash_write(start_addr, src, len);
if (!success) {
BOOT_LOG_ERR("%s: Flash write failed", __func__);
return -1;
}
return 0;
}
int flash_area_erase(const struct flash_area *fa, uint32_t off, uint32_t len)
{
if (fa->fa_device_id != FLASH_DEVICE_INTERNAL_FLASH) {
return -1;
}
if ((len % FLASH_SECTOR_SIZE) != 0 || (off % FLASH_SECTOR_SIZE) != 0) {
BOOT_LOG_ERR("%s: Not aligned on sector Offset: 0x%x Length: 0x%x",
__func__, (int)off, (int)len);
return -1;
}
const uint32_t start_addr = fa->fa_off + off;
BOOT_LOG_DBG("%s: Addr: 0x%08x Length: %d", __func__, (int)start_addr, (int)len);
if (bootloader_flash_erase_range(start_addr, len) != ESP_OK) {
BOOT_LOG_ERR("%s: Flash erase failed", __func__);
return -1;
}
#if VALIDATE_PROGRAM_OP
for (size_t i = 0; i < len; i++) {
uint8_t *val = (void *)(start_addr + i);
if (*val != 0xff) {
BOOT_LOG_ERR("%s: Erase at 0x%x Failed", __func__, (int)val);
assert(0);
}
}
#endif
return 0;
}
uint32_t flash_area_align(const struct flash_area *area)
{
static size_t align = 0;
if (align == 0) {
#ifdef CONFIG_SECURE_FLASH_ENC_ENABLED
bool flash_encryption_enabled = esp_flash_encryption_enabled();
#else
bool flash_encryption_enabled = false;
#endif
if (flash_encryption_enabled) {
align = 32;
} else {
align = 4;
}
}
return align;
}
uint8_t flash_area_erased_val(const struct flash_area *area)
{
return 0xff;
}
int flash_area_get_sectors(int fa_id, uint32_t *count,
struct flash_sector *sectors)
{
const struct flash_area *fa = prv_lookup_flash_area(fa_id);
if (fa->fa_device_id != FLASH_DEVICE_INTERNAL_FLASH) {
return -1;
}
const size_t sector_size = FLASH_SECTOR_SIZE;
uint32_t total_count = 0;
for (size_t off = 0; off < fa->fa_size; off += sector_size) {
// Note: Offset here is relative to flash area, not device
sectors[total_count].fs_off = off;
sectors[total_count].fs_size = sector_size;
total_count++;
}
*count = total_count;
return 0;
}
int flash_area_sector_from_off(uint32_t off, struct flash_sector *sector)
{
sector->fs_off = (off / FLASH_SECTOR_SIZE) * FLASH_SECTOR_SIZE;
sector->fs_size = FLASH_SECTOR_SIZE;
return 0;
}
int flash_area_get_sector(const struct flash_area *fa, uint32_t off,
struct flash_sector *sector)
{
sector->fs_off = (off / FLASH_SECTOR_SIZE) * FLASH_SECTOR_SIZE;
sector->fs_size = FLASH_SECTOR_SIZE;
return 0;
}
int flash_area_id_from_multi_image_slot(int image_index, int slot)
{
BOOT_LOG_DBG("%s", __func__);
switch (slot) {
case 0:
return FLASH_AREA_IMAGE_PRIMARY(image_index);
case 1:
return FLASH_AREA_IMAGE_SECONDARY(image_index);
}
BOOT_LOG_ERR("Unexpected Request: image_index=%d, slot=%d", image_index, slot);
return -1; /* flash_area_open will fail on that */
}
int flash_area_id_from_image_slot(int slot)
{
return flash_area_id_from_multi_image_slot(0, slot);
}
int flash_area_to_sectors(int idx, int *cnt, struct flash_area *fa)
{
return -1;
}
void mcuboot_assert_handler(const char *file, int line, const char *func)
{
ets_printf("assertion failed: file \"%s\", line %d, func: %s\n", file, line, func);
abort();
}